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[ARM] omap: make sure virtual mmio addresses are __iomem pointer-like

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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2008-09-04 14:29:01 +01:00
committed by Russell King
parent e8a91c953f
commit 0062f1048b
2 changed files with 7 additions and 7 deletions
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6
arch/arm/plat-omap/include/mach/fpga.h
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@@ -34,7 +34,7 @@ extern void omap1510_fpga_init_irq(void);
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
*/ */
/* maps in the FPGA registers and the ETHR registers */ /* maps in the FPGA registers and the ETHR registers */
#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ #define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ #define H2P2_DBG_FPGA_START 0x04000000 /* PA */
@@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
* OMAP-1510 FPGA * OMAP-1510 FPGA
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
*/ */
#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ #define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
#define OMAP1510_FPGA_SIZE SZ_4K #define OMAP1510_FPGA_SIZE SZ_4K
#define OMAP1510_FPGA_START 0x08000000 /* Physical */ #define OMAP1510_FPGA_START 0x08000000 /* PA */
/* Revision */ /* Revision */
#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) #define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)

2
arch/arm/plat-omap/include/mach/hardware.h
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@@ -89,7 +89,7 @@
#define DPLL_CTL (0xfffecf00) #define DPLL_CTL (0xfffecf00)
/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
#define DSP_CONFIG_REG_BASE (0xe1008000) #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)