net/ucc_geth: Add SGMII support for UEC GETH driver
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
fbcc0e2ce5
commit
047584ce94
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
|
||||
* Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
|
||||
*
|
||||
* Author: Shlomi Gridish <gridish@freescale.com>
|
||||
*
|
||||
@@ -193,6 +193,31 @@ struct ucc_geth {
|
||||
#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
|
||||
#define ENET_TBI_MII_TBICON 0x11 /* TBI control */
|
||||
|
||||
/* TBI MDIO register bit fields*/
|
||||
#define TBISR_LSTATUS 0x0004
|
||||
#define TBICON_CLK_SELECT 0x0020
|
||||
#define TBIANA_ASYMMETRIC_PAUSE 0x0100
|
||||
#define TBIANA_SYMMETRIC_PAUSE 0x0080
|
||||
#define TBIANA_HALF_DUPLEX 0x0040
|
||||
#define TBIANA_FULL_DUPLEX 0x0020
|
||||
#define TBICR_PHY_RESET 0x8000
|
||||
#define TBICR_ANEG_ENABLE 0x1000
|
||||
#define TBICR_RESTART_ANEG 0x0200
|
||||
#define TBICR_FULL_DUPLEX 0x0100
|
||||
#define TBICR_SPEED1_SET 0x0040
|
||||
|
||||
#define TBIANA_SETTINGS ( \
|
||||
TBIANA_ASYMMETRIC_PAUSE \
|
||||
| TBIANA_SYMMETRIC_PAUSE \
|
||||
| TBIANA_FULL_DUPLEX \
|
||||
)
|
||||
#define TBICR_SETTINGS ( \
|
||||
TBICR_PHY_RESET \
|
||||
| TBICR_ANEG_ENABLE \
|
||||
| TBICR_FULL_DUPLEX \
|
||||
| TBICR_SPEED1_SET \
|
||||
)
|
||||
|
||||
/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
|
||||
#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
|
||||
Rx */
|
||||
@@ -1188,6 +1213,7 @@ struct ucc_geth_private {
|
||||
|
||||
struct ugeth_mii_info *mii_info;
|
||||
struct phy_device *phydev;
|
||||
struct phy_device *tbiphy;
|
||||
phy_interface_t phy_interface;
|
||||
int max_speed;
|
||||
uint32_t msg_enable;
|
||||
|
Reference in New Issue
Block a user