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m68knommu: simplify ColdFire "timers" clock initialization

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The ColdFire "timers" clock setup can be simplified. There is really no
need for the flexible per-platform setup code. The clock interrupt can be
hard defined per CPU platform (in CPU include files). This makes the
actual timer code simpler.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer
2009-05-19 14:52:40 +10:00
parent f9311f2643
commit 04b75b10dc
12 changed files with 92 additions and 122 deletions
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13
arch/m68k/include/asm/m5206sim.h
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@@ -88,12 +88,19 @@
#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Generic GPIO
*/
#define MCFGPIO_PIN_MAX 8
#define MCFGPIO_IRQ_VECBASE -1
#define MCFGPIO_IRQ_MAX -1
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
@@ -117,11 +124,5 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
/*
* Let the common interrupt handler code know that the ColdFire 5206*
* family of CPU's only has a 16bit sized IMR register.
*/
#define MCFSIM_IMR_IS_16BITS
/****************************************************************************/
#endif /* m5206sim_h */

6
arch/m68k/include/asm/m5249sim.h
View File

@@ -70,6 +70,12 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* General purpose IO registers (in MBAR2).
*/

5
arch/m68k/include/asm/m5272sim.h
View File

@@ -73,6 +73,11 @@
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 69 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 70 /* Timer1, Level 7 */
/*
* Generic GPIO support

6
arch/m68k/include/asm/m5307sim.h
View File

@@ -124,6 +124,7 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
@@ -139,6 +140,11 @@
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Define the Cache register flags.

5
arch/m68k/include/asm/m5407sim.h
View File

@@ -111,6 +111,11 @@
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Define the Cache register flags.