serial: Support the EFR-register of XR1715x uarts.
The EFR (Enhenced-Features-Register) is located at a different offset than the other devices supporting UART_CAP_EFR. This change add a special setup quick to set UPF_EXAR_EFR on the port. UPF_EXAR_EFR is then used to the port type to PORT_XR17D15X since it is for sure a XR17D15X uart. Signed-off-by: Søren Holm <sgh@sgh.dk> Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
2f7861de11
commit
06315348b1
@@ -309,6 +309,13 @@ static const struct serial8250_config uart_config[] = {
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UART_FCR_T_TRIG_01,
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UART_FCR_T_TRIG_01,
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.flags = UART_CAP_FIFO | UART_CAP_RTOIE,
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.flags = UART_CAP_FIFO | UART_CAP_RTOIE,
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},
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},
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[PORT_XR17D15X] = {
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.name = "XR17D15X",
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.fifo_size = 64,
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.tx_loadsz = 64,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
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.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
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},
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};
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};
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#if defined(CONFIG_MIPS_ALCHEMY)
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#if defined(CONFIG_MIPS_ALCHEMY)
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@@ -1074,6 +1081,14 @@ static void autoconfig_16550a(struct uart_8250_port *up)
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}
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}
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serial_outp(up, UART_IER, iersave);
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serial_outp(up, UART_IER, iersave);
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/*
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* Exar uarts have EFR in a weird location
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*/
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if (up->port.flags & UPF_EXAR_EFR) {
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up->port.type = PORT_XR17D15X;
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up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
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}
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/*
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/*
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* We distinguish between 16550A and U6 16550A by counting
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* We distinguish between 16550A and U6 16550A by counting
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* how many bytes are in the FIFO.
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* how many bytes are in the FIFO.
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@@ -2417,7 +2432,10 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
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efr |= UART_EFR_CTS;
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efr |= UART_EFR_CTS;
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serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_outp(up, UART_EFR, efr);
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if (up->port.flags & UPF_EXAR_EFR)
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serial_outp(up, UART_XR_EFR, efr);
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else
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serial_outp(up, UART_EFR, efr);
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}
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}
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#ifdef CONFIG_ARCH_OMAP
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#ifdef CONFIG_ARCH_OMAP
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@@ -1101,6 +1101,15 @@ static int pci_eg20t_init(struct pci_dev *dev)
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#endif
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#endif
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}
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}
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static int
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pci_xr17c154_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_port *port, int idx)
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{
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port->flags |= UPF_EXAR_EFR;
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return pci_default_setup(priv, board, port, idx);
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}
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/* This should be in linux/pci_ids.h */
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/* This should be in linux/pci_ids.h */
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#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
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#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
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#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
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#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
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@@ -1505,6 +1514,30 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subdevice = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_timedia_setup,
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.setup = pci_timedia_setup,
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},
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},
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/*
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* Exar cards
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*/
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{
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.vendor = PCI_VENDOR_ID_EXAR,
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.device = PCI_DEVICE_ID_EXAR_XR17C152,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_xr17c154_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_EXAR,
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.device = PCI_DEVICE_ID_EXAR_XR17C154,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_xr17c154_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_EXAR,
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.device = PCI_DEVICE_ID_EXAR_XR17C158,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_xr17c154_setup,
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},
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/*
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/*
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* Xircom cards
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* Xircom cards
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*/
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*/
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@@ -46,7 +46,8 @@
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#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
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#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
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#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
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#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
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#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
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#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
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#define PORT_MAX_8250 20 /* max port ID */
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#define PORT_XR17D15X 21 /* Exar XR17D15x UART */
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#define PORT_MAX_8250 21 /* max port ID */
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/*
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/*
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* ARM specific type numbers. These are not currently guaranteed
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* ARM specific type numbers. These are not currently guaranteed
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@@ -349,6 +350,7 @@ struct uart_port {
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#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
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#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
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#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
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#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
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#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
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#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
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#define UPF_EXAR_EFR ((__force upf_t) (1 << 25))
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/* The exact UART type is known and should not be probed. */
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/* The exact UART type is known and should not be probed. */
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#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
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#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
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#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
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#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
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@@ -152,6 +152,7 @@
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* LCR=0xBF (or DLAB=1 for 16C660)
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* LCR=0xBF (or DLAB=1 for 16C660)
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*/
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*/
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#define UART_EFR 2 /* I/O: Extended Features Register */
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#define UART_EFR 2 /* I/O: Extended Features Register */
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#define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */
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#define UART_EFR_CTS 0x80 /* CTS flow control */
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#define UART_EFR_CTS 0x80 /* CTS flow control */
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#define UART_EFR_RTS 0x40 /* RTS flow control */
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#define UART_EFR_RTS 0x40 /* RTS flow control */
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#define UART_EFR_SCD 0x20 /* Special character detect */
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#define UART_EFR_SCD 0x20 /* Special character detect */
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