Merge tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
* tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: (29 commits) C6X: replace tick_nohz_stop/restart_sched_tick calls C6X: add register_cpu call C6X: deal with memblock API changes C6X: fix timer64 initialization C6X: fix layout of EMIFA registers C6X: MAINTAINERS C6X: DSCR - Device State Configuration Registers C6X: EMIF - External Memory Interface C6X: general SoC support C6X: library code C6X: headers C6X: ptrace support C6X: loadable module support C6X: cache control C6X: clocks C6X: build infrastructure C6X: syscalls C6X: interrupt handling C6X: time management C6X: signal management ...
This commit is contained in:
Linus Torvalds
40
Documentation/devicetree/bindings/c6x/clocks.txt
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40
Documentation/devicetree/bindings/c6x/clocks.txt
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C6X PLL Clock Controllers
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-------------------------
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This is a first-cut support for the SoC clock controllers. This is still
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under development and will probably change as the common device tree
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clock support is added to the kernel.
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Required properties:
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- compatible: "ti,c64x+pll"
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May also have SoC-specific value to support SoC-specific initialization
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in the driver. One of:
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"ti,c6455-pll"
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"ti,c6457-pll"
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"ti,c6472-pll"
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"ti,c6474-pll"
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- reg: base address and size of register area
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- clock-frequency: input clock frequency in hz
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Optional properties:
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- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
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- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
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- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
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Example:
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clock-controller@29a0000 {
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compatible = "ti,c6472-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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clock-frequency = <25000000>;
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ti,c64x+pll-bypass-delay = <200>;
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ti,c64x+pll-reset-delay = <12000>;
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ti,c64x+pll-lock-delay = <80000>;
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};
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127
Documentation/devicetree/bindings/c6x/dscr.txt
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127
Documentation/devicetree/bindings/c6x/dscr.txt
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Device State Configuration Registers
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------------------------------------
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TI C6X SoCs contain a region of miscellaneous registers which provide various
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function for SoC control or status. Details vary considerably among from SoC
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to SoC with no two being alike.
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In general, the Device State Configuraion Registers (DSCR) will provide one or
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more configuration registers often protected by a lock register where one or
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more key values must be written to a lock register in order to unlock the
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configuration register for writes. These configuration register may be used to
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enable (and disable in some cases) SoC pin drivers, select peripheral clock
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sources (internal or pin), etc. In some cases, a configuration register is
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write once or the individual bits are write once. In addition to device config,
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the DSCR block may provide registers which which are used to reset peripherals,
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provide device ID information, provide ethernet MAC addresses, as well as other
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miscellaneous functions.
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For device state control (enable/disable), each device control is assigned an
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id which is used by individual device drivers to control the state as needed.
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Required properties:
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- compatible: must be "ti,c64x+dscr"
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- reg: register area base and size
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Optional properties:
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NOTE: These are optional in that not all SoCs will have all properties. For
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SoCs which do support a given property, leaving the property out of the
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device tree will result in reduced functionality or possibly driver
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failure.
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- ti,dscr-devstat
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offset of the devstat register
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- ti,dscr-silicon-rev
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offset, start bit, and bitsize of silicon revision field
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- ti,dscr-rmii-resets
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offset and bitmask of RMII reset field. May have multiple tuples if more
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than one ethernet port is available.
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- ti,dscr-locked-regs
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possibly multiple tuples describing registers which are write protected by
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a lock register. Each tuple consists of the register offset, lock register
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offsset, and the key value used to unlock the register.
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- ti,dscr-kick-regs
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offset and key values of two "kick" registers used to write protect other
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registers in DSCR. On SoCs using kick registers, the first key must be
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written to the first kick register and the second key must be written to
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the second register before other registers in the area are write-enabled.
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- ti,dscr-mac-fuse-regs
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MAC addresses are contained in two registers. Each element of a MAC address
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is contained in a single byte. This property has two tuples. Each tuple has
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a register offset and four cells representing bytes in the register from
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most significant to least. The value of these four cells is the MAC byte
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index (1-6) of the byte within the register. A value of 0 means the byte
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is unused in the MAC address.
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- ti,dscr-devstate-ctl-regs
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This property describes the bitfields used to control the state of devices.
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Each tuple describes a range of identical bitfields used to control one or
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more devices (one bitfield per device). The layout of each tuple is:
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start_id num_ids reg enable disable start_bit nbits
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Where:
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start_id is device id for the first device control in the range
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num_ids is the number of device controls in the range
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reg is the offset of the register holding the control bits
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enable is the value to enable a device
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disable is the value to disable a device (0xffffffff if cannot disable)
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start_bit is the bit number of the first bit in the range
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nbits is the number of bits per device control
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- ti,dscr-devstate-stat-regs
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This property describes the bitfields used to provide device state status
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for device states controlled by the DSCR. Each tuple describes a range of
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identical bitfields used to provide status for one or more devices (one
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bitfield per device). The layout of each tuple is:
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start_id num_ids reg enable disable start_bit nbits
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Where:
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start_id is device id for the first device status in the range
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num_ids is the number of devices covered by the range
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reg is the offset of the register holding the status bits
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enable is the value indicating device is enabled
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disable is the value indicating device is disabled
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start_bit is the bit number of the first bit in the range
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nbits is the number of bits per device status
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- ti,dscr-privperm
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Offset and default value for register used to set access privilege for
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some SoC devices.
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Example:
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device-state-config-regs@2a80000 {
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compatible = "ti,c64x+dscr";
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reg = <0x02a80000 0x41000>;
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ti,dscr-devstat = <0>;
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ti,dscr-silicon-rev = <8 28 0xf>;
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ti,dscr-rmii-resets = <0x40020 0x00040000>;
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ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
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ti,dscr-devstate-ctl-regs =
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<0 12 0x40008 1 0 0 2
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12 1 0x40008 3 0 30 2
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13 2 0x4002c 1 0xffffffff 0 1>;
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ti,dscr-devstate-stat-regs =
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<0 10 0x40014 1 0 0 3
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10 2 0x40018 1 0 0 3>;
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ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
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0x704 5 6 0 0>;
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ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
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ti,dscr-kick-regs = <0x38 0x83E70B13
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0x3c 0x95A4F1E0>;
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};
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62
Documentation/devicetree/bindings/c6x/emifa.txt
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62
Documentation/devicetree/bindings/c6x/emifa.txt
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@@ -0,0 +1,62 @@
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External Memory Interface
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-------------------------
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The emifa node describes a simple external bus controller found on some C6X
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SoCs. This interface provides external busses with a number of chip selects.
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Required properties:
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- compatible: must be "ti,c64x+emifa", "simple-bus"
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- reg: register area base and size
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- #address-cells: must be 2 (chip-select + offset)
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- #size-cells: must be 1
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- ranges: mapping from EMIFA space to parent space
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Optional properties:
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- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
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- ti,emifa-burst-priority:
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Number of memory transfers after which the EMIF will elevate the priority
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of the oldest command in the command FIFO. Setting this field to 255
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disables this feature, thereby allowing old commands to stay in the FIFO
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indefinitely.
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- ti,emifa-ce-config:
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Configuration values for each of the supported chip selects.
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Example:
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emifa@70000000 {
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compatible = "ti,c64x+emifa", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x70000000 0x100>;
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ranges = <0x2 0x0 0xa0000000 0x00000008
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0x3 0x0 0xb0000000 0x00400000
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0x4 0x0 0xc0000000 0x10000000
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0x5 0x0 0xD0000000 0x10000000>;
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ti,dscr-dev-enable = <13>;
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ti,emifa-burst-priority = <255>;
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ti,emifa-ce-config = <0x00240120
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0x00240120
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0x00240122
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0x00240122>;
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flash@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x3 0x0 0x400000>;
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bank-width = <1>;
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device-width = <1>;
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partition@0 {
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reg = <0x0 0x400000>;
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label = "NOR";
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};
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};
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};
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This shows a flash chip attached to chip select 3.
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104
Documentation/devicetree/bindings/c6x/interrupt.txt
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104
Documentation/devicetree/bindings/c6x/interrupt.txt
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@@ -0,0 +1,104 @@
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C6X Interrupt Chips
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-------------------
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* C64X+ Core Interrupt Controller
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The core interrupt controller provides 16 prioritized interrupts to the
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C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
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Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
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sources coming from outside the core.
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Required properties:
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--------------------
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- compatible: Should be "ti,c64x+core-pic";
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- #interrupt-cells: <1>
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Interrupt Specifier Definition
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------------------------------
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Single cell specifying the core interrupt priority level (4-15) where
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4 is highest priority and 15 is lowest priority.
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Example
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-------
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core_pic: interrupt-controller@0 {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "ti,c64x+core-pic";
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};
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* C64x+ Megamodule Interrupt Controller
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The megamodule PIC consists of four interrupt mupliplexers each of which
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combine up to 32 interrupt inputs into a single interrupt output which
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may be cascaded into the core interrupt controller. The megamodule PIC
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has a total of 12 outputs cascading into the core interrupt controller.
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One for each core interrupt priority level. In addition to the combined
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interrupt sources, individual megamodule interrupts may be cascaded to
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the core interrupt controller. When an individual interrupt is cascaded,
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it is no longer handled through a megamodule interrupt combiner and is
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considered to have the core interrupt controller as the parent.
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Required properties:
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--------------------
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- compatible: "ti,c64x+megamod-pic"
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- interrupt-controller
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- #interrupt-cells: <1>
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- reg: base address and size of register area
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- interrupt-parent: must be core interrupt controller
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- interrupts: This should have four cells; one for each interrupt combiner.
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The cells contain the core priority interrupt to which the
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corresponding combiner output is wired.
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Optional properties:
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--------------------
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- ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
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priority interrupts. The first cell corresponds to
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core priority 4 and the last cell corresponds to
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core priority 15. The value of each cell is the
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megamodule interrupt source which is MUXed to
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the core interrupt corresponding to the cell
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position. Allowed values are 4 - 127. Mapping for
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interrupts 0 - 3 (combined interrupt sources) are
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ignored.
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Interrupt Specifier Definition
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------------------------------
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Single cell specifying the megamodule interrupt source (4-127). Note that
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interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
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use the core interrupt controller as their parent and the specifier will
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be the core priority level, not the megamodule interrupt number.
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Examples
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--------
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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interrupts = < 12 13 14 15 >;
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};
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This is a minimal example where all individual interrupts go through a
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combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
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to interrupt 13, etc.
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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interrupts = < 12 13 14 15 >;
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ti,c64x+megamod-pic-mux = < 0 0 0 0
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32 0 0 0
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0 0 0 0 >;
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};
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This the same as the first example except that megamodule interrupt 32 is
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mapped directly to core priority interrupt 8. The node using this interrupt
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must set the core controller as its interrupt parent and use 8 in the
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interrupt specifier value.
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28
Documentation/devicetree/bindings/c6x/soc.txt
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28
Documentation/devicetree/bindings/c6x/soc.txt
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@@ -0,0 +1,28 @@
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C6X System-on-Chip
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------------------
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Required properties:
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- compatible: "simple-bus"
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges
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Optional properties:
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- model: specific SoC model
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- nodes for IP blocks within SoC
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Example:
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soc {
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compatible = "simple-bus";
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model = "tms320c6455";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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...
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};
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26
Documentation/devicetree/bindings/c6x/timer64.txt
Normal file
26
Documentation/devicetree/bindings/c6x/timer64.txt
Normal file
@@ -0,0 +1,26 @@
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Timer64
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-------
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The timer64 node describes C6X event timers.
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Required properties:
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- compatible: must be "ti,c64x+timer64"
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- reg: base address and size of register region
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- interrupt-parent: interrupt controller
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- interrupts: interrupt id
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Optional properties:
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- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
|
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- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
|
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Example:
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timer0: timer@25e0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x25e0000 0x40>;
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interrupt-parent = <&megamod_pic>;
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interrupts = < 16 >;
|
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};
|
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