drm/radeon: implement bo copy callback using CP DMA (v2)
Lighter weight than using the 3D engine. v2: fix ring count Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3144,6 +3144,87 @@ int r600_copy_blit(struct radeon_device *rdev,
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return 0;
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return 0;
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}
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}
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/**
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* r600_copy_cpdma - copy pages using the CP DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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*
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* Copy GPU paging using the CP DMA engine (r6xx+).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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int r600_copy_cpdma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence)
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{
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struct radeon_semaphore *sem = NULL;
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int ring_index = rdev->asic->copy.blit_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_bytes, cur_size_in_bytes, tmp;
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int i, num_loops;
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int r = 0;
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r = radeon_semaphore_create(rdev, &sem);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return r;
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}
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size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
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num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
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r = radeon_ring_lock(rdev, ring, num_loops * 6 + 21);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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return r;
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}
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if (radeon_fence_need_sync(*fence, ring->idx)) {
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radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
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ring->idx);
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radeon_fence_note_sync(*fence, ring->idx);
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} else {
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radeon_semaphore_free(rdev, &sem, NULL);
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}
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for (i = 0; i < num_loops; i++) {
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cur_size_in_bytes = size_in_bytes;
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if (cur_size_in_bytes > 0x1fffff)
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cur_size_in_bytes = 0x1fffff;
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size_in_bytes -= cur_size_in_bytes;
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tmp = upper_32_bits(src_offset) & 0xff;
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if (size_in_bytes == 0)
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tmp |= PACKET3_CP_DMA_CP_SYNC;
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radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
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radeon_ring_write(ring, src_offset & 0xffffffff);
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radeon_ring_write(ring, tmp);
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radeon_ring_write(ring, dst_offset & 0xffffffff);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, cur_size_in_bytes);
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src_offset += cur_size_in_bytes;
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dst_offset += cur_size_in_bytes;
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}
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
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radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
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r = radeon_fence_emit(rdev, fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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radeon_ring_unlock_commit(rdev, ring);
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radeon_semaphore_free(rdev, &sem, *fence);
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return r;
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}
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/**
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/**
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* r600_copy_dma - copy pages using the DMA engine
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* r600_copy_dma - copy pages using the DMA engine
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*
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*
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@ -602,6 +602,7 @@
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#define L2_BUSY (1 << 0)
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#define L2_BUSY (1 << 0)
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#define WAIT_UNTIL 0x8040
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#define WAIT_UNTIL 0x8040
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#define WAIT_CP_DMA_IDLE_bit (1 << 8)
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#define WAIT_2D_IDLE_bit (1 << 14)
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#define WAIT_2D_IDLE_bit (1 << 14)
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#define WAIT_3D_IDLE_bit (1 << 15)
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#define WAIT_3D_IDLE_bit (1 << 15)
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#define WAIT_2D_IDLECLEAN_bit (1 << 16)
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#define WAIT_2D_IDLECLEAN_bit (1 << 16)
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@ -340,6 +340,9 @@ int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
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int r600_copy_blit(struct radeon_device *rdev,
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int r600_copy_blit(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages, struct radeon_fence **fence);
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unsigned num_gpu_pages, struct radeon_fence **fence);
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int r600_copy_cpdma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages, struct radeon_fence **fence);
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int r600_copy_dma(struct radeon_device *rdev,
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int r600_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages, struct radeon_fence **fence);
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unsigned num_gpu_pages, struct radeon_fence **fence);
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