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[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.

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The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
opposes it being called that) where invalid instructions in the same
I-cache line worth of instructions being fetched may case spurious
exceptions.

The workaround for this was only enabled for E9000 cores; enable it also
for all RM7000-based platforms.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-07-05 08:14:21 +01:00
parent 9349075a15
commit 075c733e19
1 changed files with 10 additions and 6 deletions
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16
include/asm-mips/war.h
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@@ -177,18 +177,22 @@
#endif #endif
/* /*
* The RM9000 has a bug (though PMC-Sierra opposes it being called that) * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
* where invalid instructions in the same I-cache line worth of instructions * opposes it being called that) where invalid instructions in the same
* being fetched may case spurious exceptions. * I-cache line worth of instructions being fetched may case spurious
* exceptions.
*/ */
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \
defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \
defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
#define ICACHE_REFILLS_WORKAROUND_WAR 1 #define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif #endif
/* /*
* ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
* may cause ll / sc and lld / scd sequences to execute non-atomically. * may cause ll / sc and lld / scd sequences to execute non-atomically.
*/ */
#ifdef CONFIG_SGI_IP27 #ifdef CONFIG_SGI_IP27