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x86: Use section .data.page_aligned for the idt_table.

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The .data.idt section is just squashed into the .data.page_aligned
output section by the linker script anyway, so it might as well be in
the .data.page_aligned section.

This eliminates all references to .data.idt on x86.

Signed-off-by: Tim Abbott <tabbott@ksplice.com>
Cc: Ingo Molnar <mingo@redhat.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Tim Abbott
2009-09-16 16:44:29 -04:00
committed by H. Peter Anvin
parent 4ae59b916d
commit 07e81d6160
2 changed files with 2 additions and 5 deletions
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6
arch/x86/kernel/traps.c
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@@ -73,11 +73,9 @@ char ignore_fpu_irq;
/* /*
* The IDT has to be page-aligned to simplify the Pentium * The IDT has to be page-aligned to simplify the Pentium
* F0 0F bug workaround.. We have a special link segment * F0 0F bug workaround.
* for this.
*/ */
gate_desc idt_table[NR_VECTORS] gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
__attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, };
#endif #endif
DECLARE_BITMAP(used_vectors, NR_VECTORS); DECLARE_BITMAP(used_vectors, NR_VECTORS);

1
arch/x86/kernel/vmlinux.lds.S
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@@ -112,7 +112,6 @@ SECTIONS
#endif #endif
PAGE_ALIGNED_DATA(PAGE_SIZE) PAGE_ALIGNED_DATA(PAGE_SIZE)
*(.data.idt)
CACHELINE_ALIGNED_DATA(CONFIG_X86_L1_CACHE_BYTES) CACHELINE_ALIGNED_DATA(CONFIG_X86_L1_CACHE_BYTES)