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[ARM] mm: enable sparsemem on clps7500 and RiscPC

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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2008-10-01 17:11:06 +01:00
committed by Russell King
parent b7a69ac303
commit 07f841b7c5
4 changed files with 35 additions and 3 deletions
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20
arch/arm/include/asm/sparsemem.h
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@@ -3,8 +3,22 @@
#include <asm/memory.h>
#define MAX_PHYSADDR_BITS 32
#define MAX_PHYSMEM_BITS 32
#define SECTION_SIZE_BITS NODE_MEM_SIZE_BITS
/*
* Two definitions are required for sparsemem:
*
* MAX_PHYSMEM_BITS: The number of physical address bits required
* to address the last byte of memory.
*
* SECTION_SIZE_BITS: The number of physical address bits to cover
* the maximum amount of memory in a section.
*
* Eg, if you have 2 banks of up to 64MB at 0x80000000, 0x84000000,
* then MAX_PHYSMEM_BITS is 32, SECTION_SIZE_BITS is 26.
*
* Define these in your mach/memory.h.
*/
#if !defined(SECTION_SIZE_BITS) || !defined(MAX_PHYSMEM_BITS)
#error Sparsemem is not supported on this platform
#endif
#endif