x86: Move calibrate_cpu to tsc.c
Move the code where it's only user is. Also we need to look whether this hardwired hackery might interfere with perfcounters. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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08047c4f17
@ -57,6 +57,4 @@ extern void time_init(void);
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#endif /* CONFIG_PARAVIRT */
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#endif /* CONFIG_PARAVIRT */
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extern unsigned long __init calibrate_cpu(void);
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#endif /* _ASM_X86_TIME_H */
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#endif /* _ASM_X86_TIME_H */
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@ -21,7 +21,6 @@
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#include <asm/timer.h>
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#include <asm/timer.h>
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#include <asm/hpet.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#include <asm/time.h>
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#include <asm/nmi.h>
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#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC)
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#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC)
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int timer_ack;
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int timer_ack;
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@ -21,7 +21,6 @@
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#include <asm/timer.h>
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#include <asm/timer.h>
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#include <asm/hpet.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#include <asm/time.h>
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#include <asm/nmi.h>
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#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC)
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#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC)
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int timer_ack;
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int timer_ack;
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@ -84,56 +83,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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/*
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* calibrate_cpu is used on systems with fixed rate TSCs to determine
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* processor frequency
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*/
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#define TICK_COUNT 100000000
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unsigned long __init calibrate_cpu(void)
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{
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int tsc_start, tsc_now;
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int i, no_ctr_free;
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unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
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unsigned long flags;
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for (i = 0; i < 4; i++)
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if (avail_to_resrv_perfctr_nmi_bit(i))
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break;
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no_ctr_free = (i == 4);
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if (no_ctr_free) {
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WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
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"cpu_khz value may be incorrect.\n");
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i = 3;
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rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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rdmsrl(MSR_K7_PERFCTR3, pmc3);
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} else {
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reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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local_irq_save(flags);
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/* start measuring cycles, incrementing from 0 */
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wrmsrl(MSR_K7_PERFCTR0 + i, 0);
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wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
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rdtscl(tsc_start);
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do {
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rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
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tsc_now = get_cycles();
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} while ((tsc_now - tsc_start) < TICK_COUNT);
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local_irq_restore(flags);
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if (no_ctr_free) {
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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wrmsrl(MSR_K7_PERFCTR3, pmc3);
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wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
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} else {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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return pmc_now * tsc_khz / (tsc_now - tsc_start);
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}
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static struct irqaction irq0 = {
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER,
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@ -17,6 +17,7 @@
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#include <asm/time.h>
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#include <asm/time.h>
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#include <asm/delay.h>
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#include <asm/delay.h>
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#include <asm/hypervisor.h>
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#include <asm/hypervisor.h>
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#include <asm/nmi.h>
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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EXPORT_SYMBOL(cpu_khz);
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EXPORT_SYMBOL(cpu_khz);
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@ -852,6 +853,60 @@ static void __init init_tsc_clocksource(void)
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clocksource_register(&clocksource_tsc);
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clocksource_register(&clocksource_tsc);
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}
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}
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#ifdef CONFIG_X86_64
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/*
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* calibrate_cpu is used on systems with fixed rate TSCs to determine
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* processor frequency
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*/
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#define TICK_COUNT 100000000
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static unsigned long __init calibrate_cpu(void)
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{
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int tsc_start, tsc_now;
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int i, no_ctr_free;
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unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
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unsigned long flags;
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for (i = 0; i < 4; i++)
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if (avail_to_resrv_perfctr_nmi_bit(i))
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break;
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no_ctr_free = (i == 4);
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if (no_ctr_free) {
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WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
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"cpu_khz value may be incorrect.\n");
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i = 3;
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rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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rdmsrl(MSR_K7_PERFCTR3, pmc3);
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} else {
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reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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local_irq_save(flags);
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/* start measuring cycles, incrementing from 0 */
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wrmsrl(MSR_K7_PERFCTR0 + i, 0);
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wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
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rdtscl(tsc_start);
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do {
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rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
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tsc_now = get_cycles();
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} while ((tsc_now - tsc_start) < TICK_COUNT);
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local_irq_restore(flags);
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if (no_ctr_free) {
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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wrmsrl(MSR_K7_PERFCTR3, pmc3);
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wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
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} else {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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return pmc_now * tsc_khz / (tsc_now - tsc_start);
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}
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#else
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static inline unsigned long calibrate_cpu(void) { return cpu_khz; }
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#endif
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void __init tsc_init(void)
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void __init tsc_init(void)
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{
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{
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u64 lpj;
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u64 lpj;
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@ -870,11 +925,9 @@ void __init tsc_init(void)
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return;
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return;
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}
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}
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#ifdef CONFIG_X86_64
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if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
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if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
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(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
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(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
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cpu_khz = calibrate_cpu();
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cpu_khz = calibrate_cpu();
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#endif
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printk("Detected %lu.%03lu MHz processor.\n",
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printk("Detected %lu.%03lu MHz processor.\n",
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(unsigned long)cpu_khz / 1000,
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(unsigned long)cpu_khz / 1000,
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