[SPARC64]: Replace cheetah+ code patching with variables.
Instead of code patching to handle the page size fields in the context registers, just use variables from which we get the proper values. Signed-off-by: David S. Miller <davem@davemloft.net>
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@@ -325,23 +325,7 @@ cheetah_tlb_fixup:
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1: sethi %hi(tlb_type), %g1
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stw %g2, [%g1 + %lo(tlb_type)]
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
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ba,pt %xcc, 2f
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nop
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1: /* Patch context register writes to support nucleus page
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* size correctly.
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*/
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call cheetah_plus_patch_etrap
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nop
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call cheetah_plus_patch_rtrap
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nop
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call cheetah_plus_patch_fpdis
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nop
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call cheetah_plus_patch_winfixup
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nop
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2: /* Patch copy/page operations to cheetah optimized versions. */
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/* Patch copy/page operations to cheetah optimized versions. */
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call cheetah_patch_copyops
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nop
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call cheetah_patch_copy_page
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@@ -484,20 +468,13 @@ spitfire_vpte_base:
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call prom_set_trap_table
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sethi %hi(sparc64_ttable_tl0), %o0
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
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ba,pt %xcc, 2f
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nop
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1: /* Start using proper page size encodings in ctx register. */
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sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3
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/* Start using proper page size encodings in ctx register. */
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sethi %hi(sparc64_kern_pri_context), %g3
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ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
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mov PRIMARY_CONTEXT, %g1
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sllx %g3, 32, %g3
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sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
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or %g3, %g2, %g3
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stxa %g3, [%g1] ASI_DMMU
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stxa %g2, [%g1] ASI_DMMU
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membar #Sync
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2:
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rdpr %pstate, %o1
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or %o1, PSTATE_IE, %o1
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wrpr %o1, 0, %pstate
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