[SPARC64]: Replace cheetah+ code patching with variables.
Instead of code patching to handle the page size fields in the context registers, just use variables from which we get the proper values. Signed-off-by: David S. Miller <davem@davemloft.net>
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@@ -256,9 +256,8 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
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brnz,pn %l3, kern_rtt
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mov PRIMARY_CONTEXT, %l7
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ldxa [%l7 + %l7] ASI_DMMU, %l0
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cplus_rtrap_insn_1:
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sethi %hi(0), %l1
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sllx %l1, 32, %l1
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sethi %hi(sparc64_kern_pri_nuc_bits), %l1
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ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
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or %l0, %l1, %l0
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stxa %l0, [%l7] ASI_DMMU
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flush %g6
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@@ -345,21 +344,3 @@ kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
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wr %g0, FPRS_DU, %fprs
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ba,pt %xcc, rt_continue
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stb %l5, [%g6 + TI_FPDEPTH]
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cplus_rinsn_1:
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sethi %uhi(CTX_CHEETAH_PLUS_NUC), %l1
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.globl cheetah_plus_patch_rtrap
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cheetah_plus_patch_rtrap:
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/* We configure the dTLB512_0 for 4MB pages and the
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* dTLB512_1 for 8K pages when in context zero.
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*/
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sethi %hi(cplus_rinsn_1), %o0
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sethi %hi(cplus_rtrap_insn_1), %o2
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lduw [%o0 + %lo(cplus_rinsn_1)], %o1
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or %o2, %lo(cplus_rtrap_insn_1), %o2
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stw %o1, [%o2]
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flush %o2
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retl
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nop
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