tg3: Allow WOL for phylib controlled Broadcom phys
This patch allows WOL to be enabled for Broadcom phys under phylib control. The only exception is the AC131, which has a completely different register set. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1963,7 +1963,7 @@ static int tg3_halt_cpu(struct tg3 *, u32);
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static int tg3_nvram_lock(struct tg3 *);
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static int tg3_nvram_lock(struct tg3 *);
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static void tg3_nvram_unlock(struct tg3 *);
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static void tg3_nvram_unlock(struct tg3 *);
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static void tg3_power_down_phy(struct tg3 *tp)
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static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
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{
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{
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u32 val;
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u32 val;
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@ -1986,10 +1986,15 @@ static void tg3_power_down_phy(struct tg3 *tp)
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tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
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tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
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udelay(40);
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udelay(40);
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return;
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return;
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} else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
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} else if (do_low_power) {
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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tg3_writephy(tp, MII_TG3_AUX_CTRL,
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MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
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MII_TG3_AUXCTL_PCTL_100TX_LPWR |
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MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
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MII_TG3_AUXCTL_PCTL_VREG_11V);
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}
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}
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/* The PHY should not be powered down on some chips because
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/* The PHY should not be powered down on some chips because
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@ -2052,7 +2057,7 @@ static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
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static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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{
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{
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u32 misc_host_ctrl;
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u32 misc_host_ctrl;
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bool device_should_wake;
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bool device_should_wake, do_low_power;
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/* Make sure register accesses (indirect or otherwise)
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/* Make sure register accesses (indirect or otherwise)
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* will function correctly.
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* will function correctly.
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@ -2091,10 +2096,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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(tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
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(tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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do_low_power = false;
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if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
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if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
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!tp->link_config.phy_is_low_power) {
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!tp->link_config.phy_is_low_power) {
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struct phy_device *phydev;
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struct phy_device *phydev;
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u32 advertising;
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u32 phyid, advertising;
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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@ -2124,8 +2130,19 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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phydev->advertising = advertising;
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phydev->advertising = advertising;
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phy_start_aneg(phydev);
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phy_start_aneg(phydev);
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phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
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if (phyid != TG3_PHY_ID_BCMAC131) {
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phyid &= TG3_PHY_OUI_MASK;
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if (phyid == TG3_PHY_OUI_1 &&
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phyid == TG3_PHY_OUI_2 &&
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phyid == TG3_PHY_OUI_3)
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do_low_power = true;
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}
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}
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}
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} else {
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} else {
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do_low_power = false;
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if (tp->link_config.phy_is_low_power == 0) {
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if (tp->link_config.phy_is_low_power == 0) {
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tp->link_config.phy_is_low_power = 1;
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tp->link_config.phy_is_low_power = 1;
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tp->link_config.orig_speed = tp->link_config.speed;
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tp->link_config.orig_speed = tp->link_config.speed;
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@ -2169,7 +2186,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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u32 mac_mode;
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u32 mac_mode;
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
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if (do_low_power) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
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udelay(40);
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udelay(40);
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}
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}
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@ -2277,7 +2294,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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if (!(device_should_wake) &&
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if (!(device_should_wake) &&
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!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
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!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
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!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
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!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
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tg3_power_down_phy(tp);
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tg3_power_down_phy(tp, do_low_power);
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tg3_frob_aux_power(tp);
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tg3_frob_aux_power(tp);
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@ -1795,6 +1795,11 @@
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#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
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#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
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#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
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#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
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#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
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#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
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#define MII_TG3_AUXCTL_MISC_WREN 0x8000
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#define MII_TG3_AUXCTL_MISC_WREN 0x8000
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#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
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#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
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#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
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#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
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@ -2590,7 +2595,10 @@ struct tg3 {
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#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
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#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
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#define TG3_PHY_ID_BCM50610 0x143bd60
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#define TG3_PHY_ID_BCM50610 0x143bd60
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#define TG3_PHY_ID_BCMAC131 0x143bc70
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#define TG3_PHY_ID_BCMAC131 0x143bc70
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#define TG3_PHY_OUI_MASK 0xfffffc00
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#define TG3_PHY_OUI_1 0x00206000
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#define TG3_PHY_OUI_2 0x0143bc00
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#define TG3_PHY_OUI_3 0x03625c00
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u32 led_ctrl;
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u32 led_ctrl;
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u32 phy_otp;
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u32 phy_otp;
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