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MIPS: Alchemy: RTC counter clocksource / clockevent support.

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Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device.  As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.

If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
2008-12-21 09:26:23 +01:00
committed by Ralf Baechle
parent 779e7d41ad
commit 0c694de12b
5 changed files with 143 additions and 181 deletions
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6
arch/mips/kernel/cpu-probe.c
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@@ -96,6 +96,9 @@ int allow_au1k_wait;
static void au1k_wait(void)
{
if (!allow_au1k_wait)
return;
/* using the wait instruction makes CP0 counter unusable */
__asm__(" .set mips3 \n"
" cache 0x14, 0(%0) \n"
@@ -186,8 +189,7 @@ void __init check_wait(void)
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
if (allow_au1k_wait)
cpu_wait = au1k_wait;
cpu_wait = au1k_wait;
break;
case CPU_20KC:
/*