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Protect manipulation of c0_status against preemption and multithreading.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2005-10-06 17:39:32 +01:00
parent 8afcb5d829
commit 101b3531a6
2 changed files with 47 additions and 12 deletions
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39
arch/mips/kernel/ptrace.c
View File

@@ -33,6 +33,7 @@
#include <asm/dsp.h> #include <asm/dsp.h>
#include <asm/fpu.h> #include <asm/fpu.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/system.h> #include <asm/system.h>
@@ -126,10 +127,21 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
__put_user (child->thread.fpu.hard.fcr31, data + 64); __put_user (child->thread.fpu.hard.fcr31, data + 64);
flags = read_c0_status(); preempt_disable();
__enable_fpu(); if (cpu_has_mipsmt) {
__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); unsigned int vpflags = dvpe();
write_c0_status(flags); flags = read_c0_status();
__enable_fpu();
__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
write_c0_status(flags);
evpe(vpflags);
} else {
flags = read_c0_status();
__enable_fpu();
__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
write_c0_status(flags);
}
preempt_enable();
__put_user (tmp, data + 65); __put_user (tmp, data + 65);
} else { } else {
__put_user (child->thread.fpu.soft.fcr31, data + 64); __put_user (child->thread.fpu.soft.fcr31, data + 64);
@@ -284,10 +296,21 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
if (!cpu_has_fpu) if (!cpu_has_fpu)
break; break;
flags = read_c0_status(); preempt_disable();
__enable_fpu(); if (cpu_has_mipsmt) {
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); unsigned int vpflags = dvpe();
write_c0_status(flags); flags = read_c0_status();
__enable_fpu();
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
write_c0_status(flags);
evpe(vpflags);
} else {
flags = read_c0_status();
__enable_fpu();
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
write_c0_status(flags);
}
preempt_enable();
break; break;
} }
case DSP_BASE ... DSP_BASE + 5: { case DSP_BASE ... DSP_BASE + 5: {

20
arch/mips/kernel/ptrace32.c
View File

@@ -29,6 +29,7 @@
#include <asm/dsp.h> #include <asm/dsp.h>
#include <asm/fpu.h> #include <asm/fpu.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/system.h> #include <asm/system.h>
@@ -191,10 +192,21 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
if (!cpu_has_fpu) if (!cpu_has_fpu)
break; break;
flags = read_c0_status(); preempt_disable();
__enable_fpu(); if (cpu_has_mipsmt) {
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); unsigned int vpflags = dvpe();
write_c0_status(flags); flags = read_c0_status();
__enable_fpu();
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
write_c0_status(flags);
evpe(vpflags);
} else {
flags = read_c0_status();
__enable_fpu();
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
write_c0_status(flags);
}
preempt_enable();
break; break;
} }
case DSP_BASE ... DSP_BASE + 5: case DSP_BASE ... DSP_BASE + 5: