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ath9k_hw: fix pll clock setting for 5ghz on AR9003

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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Felix Fietkau
2010-04-26 15:04:30 -04:00
committed by John W. Linville
parent 2fcb913173
commit 14bc110463
1 changed files with 1 additions and 10 deletions
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9
drivers/net/wireless/ath/ath9k/ar9003_phy.c
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@@ -375,15 +375,6 @@ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
else if (chan && IS_CHAN_QUARTER_RATE(chan)) else if (chan && IS_CHAN_QUARTER_RATE(chan))
pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
if (chan && IS_CHAN_5GHZ(chan)) {
pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
/*
* When doing fast clock, set PLL to 0x142c
*/
if (IS_CHAN_A_5MHZ_SPACED(chan))
pll = 0x142c;
} else
pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
return pll; return pll;