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MIPS: Add identifiers for Octeon II CPUs.

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Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1662/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
2010-10-07 16:03:43 -07:00
committed by Ralf Baechle
parent b8db85b5b5
commit 1584d7f2d5
1 changed files with 2 additions and 1 deletions
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3
arch/mips/include/asm/cpu.h
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@@ -131,6 +131,7 @@
#define PRID_IMP_CAVIUM_CN56XX 0x0400 #define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600 #define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700 #define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
/* /*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -231,7 +232,7 @@ enum cpu_type_enum {
* MIPS64 class processors * MIPS64 class processors
*/ */
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
CPU_LAST CPU_LAST
}; };