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[MIPS] Make support for weakly ordered LL/SC a config option.

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None of weakly ordered processor supported in tree need this but it seems
like this could change ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-07-14 13:24:05 +01:00
parent ed203dadcd
commit 17099b1142
7 changed files with 59 additions and 38 deletions
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10
include/asm-mips/bitops.h
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@@ -38,8 +38,8 @@
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
#define smp_mb__before_clear_bit() smp_llsc_mb()
#define smp_mb__after_clear_bit() smp_llsc_mb()
/*
* set_bit - Atomically set a bit in memory
@@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr,
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return res != 0;
}
@@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr,
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return res != 0;
}
@@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr,
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return res != 0;
}