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[MIPS] Make support for weakly ordered LL/SC a config option.

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None of weakly ordered processor supported in tree need this but it seems
like this could change ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-07-14 13:24:05 +01:00
parent ed203dadcd
commit 17099b1142
7 changed files with 59 additions and 38 deletions
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8
include/asm-mips/system.h
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@@ -117,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@@ -165,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@@ -246,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@@ -352,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}