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x86: remove extra barriers from load_gs_base()

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Impact: optimization

mb() generates an mfence instruction, which is not needed here.  Only
a compiler barrier is needed, and that is handled by the memory clobber
in the wrmsrl function.

Signed-off-by: Brian Gerst <brgerst@gmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Brian Gerst
2009-01-27 12:56:48 +09:00
committed by Tejun Heo
parent b2d2f4312b
commit 1825b8edc2
1 changed files with 0 additions and 3 deletions
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3
arch/x86/include/asm/processor.h
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@@ -397,10 +397,7 @@ DECLARE_PER_CPU(char *, irq_stack_ptr);
static inline void load_gs_base(int cpu) static inline void load_gs_base(int cpu)
{ {
/* Memory clobbers used to order pda/percpu accesses */
mb();
wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
mb();
} }
#endif #endif