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[ARM] Feroceon: don't disable BPU on boot

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On Feroceon platforms that have a branch prediction unit, bit 11 of the
cp15 control register controls the BPU.  This patch keeps the old value
of this bit instead of always clearing it.

Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Saeed Bishara
2008-07-02 06:06:32 -11:00
committed by Nicolas Pitre
parent 2e1117d307
commit 188237e28d
1 changed files with 5 additions and 4 deletions
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9
arch/arm/mm/proc-feroceon.S
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@@ -493,14 +493,15 @@ __feroceon_setup:
.size __feroceon_setup, . - __feroceon_setup .size __feroceon_setup, . - __feroceon_setup
/* /*
* R * B
* .RVI ZFRS BLDP WCAM * R P
* .011 0001 ..11 0101 * .RVI UFRS BLDP WCAM
* .011 .001 ..11 0101
* *
*/ */
.type feroceon_crval, #object .type feroceon_crval, #object
feroceon_crval: feroceon_crval:
crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
__INITDATA __INITDATA