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@@ -236,9 +236,8 @@ static void ath9k_ani_restart(struct ath_hw *ah)
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return;
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aniState = ah->curani;
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aniState->listenTime = 0;
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if (ah->has_hw_phycounters) {
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if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
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aniState->ofdmPhyErrBase = 0;
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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@@ -265,7 +264,7 @@ static void ath9k_ani_restart(struct ath_hw *ah)
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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}
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aniState->ofdmPhyErrCount = 0;
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aniState->cckPhyErrCount = 0;
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}
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@@ -530,18 +529,12 @@ void ath9k_ani_reset(struct ath_hw *ah)
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if (aniState->firstepLevel != 0)
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel);
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if (ah->has_hw_phycounters) {
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ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
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~ATH9K_RX_FILTER_PHYERR);
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ath9k_ani_restart(ah);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
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} else {
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ath9k_ani_restart(ah);
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ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
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ATH9K_RX_FILTER_PHYERR);
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}
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}
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void ath9k_hw_ani_monitor(struct ath_hw *ah,
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@@ -550,6 +543,8 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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{
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struct ar5416AniState *aniState;
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int32_t listenTime;
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u32 phyCnt1, phyCnt2;
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u32 ofdmPhyErrCnt, cckPhyErrCnt;
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if (!DO_ANI(ah))
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return;
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@@ -566,10 +561,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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aniState->listenTime += listenTime;
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if (ah->has_hw_phycounters) {
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u32 phyCnt1, phyCnt2;
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u32 ofdmPhyErrCnt, cckPhyErrCnt;
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
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@@ -609,7 +600,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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ah->stats.ast_ani_cckerrs +=
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cckPhyErrCnt - aniState->cckPhyErrCount;
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aniState->cckPhyErrCount = cckPhyErrCnt;
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}
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if (aniState->listenTime > 5 * ah->aniperiod) {
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if (aniState->ofdmPhyErrCount <= aniState->listenTime *
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@@ -632,11 +622,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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}
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}
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bool ath9k_hw_phycounters(struct ath_hw *ah)
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{
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return ah->has_hw_phycounters ? true : false;
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}
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void ath9k_enable_mib_counters(struct ath_hw *ah)
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{
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DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
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@@ -781,9 +766,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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{
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int i;
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DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
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ah->has_hw_phycounters = 1;
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DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n");
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memset(ah->ani, 0, sizeof(ah->ani));
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for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
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@@ -799,14 +782,12 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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ATH9K_ANI_CCK_WEAK_SIG_THR;
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ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
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ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
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if (ah->has_hw_phycounters) {
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ah->ani[i].ofdmPhyErrBase =
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AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
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ah->ani[i].cckPhyErrBase =
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AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
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}
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}
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if (ah->has_hw_phycounters) {
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"Setting OfdmErrBase = 0x%08x\n",
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ah->ani[0].ofdmPhyErrBase);
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@@ -816,7 +797,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
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ath9k_enable_mib_counters(ah);
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}
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ah->aniperiod = ATH9K_ANI_PERIOD;
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if (ah->config.enable_ani)
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ah->proc_phyerr |= HAL_PROCESS_ANI;
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@@ -826,9 +807,7 @@ void ath9k_hw_ani_disable(struct ath_hw *ah)
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{
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DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n");
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if (ah->has_hw_phycounters) {
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ath9k_hw_disable_mib_counters(ah);
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REG_WRITE(ah, AR_PHY_ERR_1, 0);
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REG_WRITE(ah, AR_PHY_ERR_2, 0);
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}
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}
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