[MMC] sdhci: proper timeout handling
Use the give timeout clock and calculate a proper timeout instead of using the maximum at all times. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
committed by
Russell King
parent
e16514d8d8
commit
1c8cde92fa
@@ -128,9 +128,6 @@ static void sdhci_init(struct sdhci_host *host)
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writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
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writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
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writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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/* This is unknown magic. */
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writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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}
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}
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static void sdhci_activate_led(struct sdhci_host *host)
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static void sdhci_activate_led(struct sdhci_host *host)
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@@ -274,6 +271,8 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
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static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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{
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{
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u16 mode;
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u16 mode;
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u8 count;
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unsigned target_timeout, current_timeout;
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WARN_ON(host->data);
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WARN_ON(host->data);
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@@ -287,6 +286,37 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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DBG("tsac %d ms nsac %d clk\n",
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DBG("tsac %d ms nsac %d clk\n",
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data->timeout_ns / 1000000, data->timeout_clks);
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data->timeout_ns / 1000000, data->timeout_clks);
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/* timeout in us */
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target_timeout = data->timeout_ns / 1000 +
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data->timeout_clks / host->clock;
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/*
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* Figure out needed cycles.
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* We do this in steps in order to fit inside a 32 bit int.
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* The first step is the minimum timeout, which will have a
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* minimum resolution of 6 bits:
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* (1) 2^13*1000 > 2^22,
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* (2) host->timeout_clk < 2^16
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* =>
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* (1) / (2) > 2^6
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*/
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count = 0;
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current_timeout = (1 << 13) * 1000 / host->timeout_clk;
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while (current_timeout < target_timeout) {
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count++;
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current_timeout <<= 1;
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if (count >= 0xF)
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break;
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}
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if (count >= 0xF) {
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printk(KERN_WARNING "%s: Too large timeout requested!\n",
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mmc_hostname(host->mmc));
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count = 0xE;
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}
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writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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mode = SDHCI_TRNS_BLK_CNT_EN;
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mode = SDHCI_TRNS_BLK_CNT_EN;
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if (data->blocks > 1)
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if (data->blocks > 1)
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mode |= SDHCI_TRNS_MULTI;
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mode |= SDHCI_TRNS_MULTI;
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@@ -1096,6 +1126,17 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
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}
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}
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host->max_clk *= 1000000;
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host->max_clk *= 1000000;
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host->timeout_clk =
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(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
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if (host->timeout_clk == 0) {
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printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
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"frequency.\n", host->slot_descr);
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ret = -ENODEV;
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goto unmap;
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}
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if (caps & SDHCI_TIMEOUT_CLK_UNIT)
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host->timeout_clk *= 1000;
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/*
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/*
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* Set host parameters.
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* Set host parameters.
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*/
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*/
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@@ -125,6 +125,9 @@
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/* 3E-3F reserved */
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/* 3E-3F reserved */
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_CAN_DO_DMA 0x00400000
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#define SDHCI_CAN_DO_DMA 0x00400000
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@@ -156,6 +159,7 @@ struct sdhci_host {
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#define SDHCI_USE_DMA (1<<0)
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#define SDHCI_USE_DMA (1<<0)
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unsigned int max_clk; /* Max possible freq (MHz) */
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unsigned int max_clk; /* Max possible freq (MHz) */
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unsigned int timeout_clk; /* Timeout freq (KHz) */
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unsigned int clock; /* Current clock (MHz) */
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unsigned int clock; /* Current clock (MHz) */
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unsigned short power; /* Current voltage */
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unsigned short power; /* Current voltage */
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