Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
This commit is contained in:
Linus Torvalds
325
arch/mips/pci/ops-au1000.c
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325
arch/mips/pci/ops-au1000.c
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/*
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* BRIEF MODULE DESCRIPTION
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* Alchemy/AMD Au1x00 pci support.
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*
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* Copyright 2001,2002,2003 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Support for all devices (greater than 16) added by David Gathright.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/vmalloc.h>
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#include <asm/mach-au1x00/au1000.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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int (*board_pci_idsel)(unsigned int devsel, int assert);
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/* CP0 hazard avoidance. */
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#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
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"nop; nop; nop; nop;\t" \
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".set reorder\n\t")
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void mod_wired_entry(int entry, unsigned long entrylo0,
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unsigned long entrylo1, unsigned long entryhi,
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unsigned long pagemask)
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{
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unsigned long old_pagemask;
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unsigned long old_ctx;
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi() & 0xff;
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old_pagemask = read_c0_pagemask();
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write_c0_index(entry);
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BARRIER;
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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BARRIER;
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tlb_write_indexed();
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BARRIER;
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write_c0_entryhi(old_ctx);
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BARRIER;
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write_c0_pagemask(old_pagemask);
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}
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struct vm_struct *pci_cfg_vm;
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static int pci_cfg_wired_entry;
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static int first_cfg = 1;
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unsigned long last_entryLo0, last_entryLo1;
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static int config_access(unsigned char access_type, struct pci_bus *bus,
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unsigned int dev_fn, unsigned char where,
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u32 * data)
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{
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#if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
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unsigned int device = PCI_SLOT(dev_fn);
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unsigned int function = PCI_FUNC(dev_fn);
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unsigned long offset, status;
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unsigned long cfg_base;
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unsigned long flags;
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int error = PCIBIOS_SUCCESSFUL;
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unsigned long entryLo0, entryLo1;
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if (device > 19) {
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*data = 0xffffffff;
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return -1;
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}
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local_irq_save(flags);
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au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
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Au1500_PCI_STATCMD);
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au_sync_udelay(1);
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/*
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* We can't ioremap the entire pci config space because it's
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* too large. Nor can we call ioremap dynamically because some
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* device drivers use the pci config routines from within
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* interrupt handlers and that becomes a problem in get_vm_area().
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* We use one wired tlb to handle all config accesses for all
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* busses. To improve performance, if the current device
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* is the same as the last device accessed, we don't touch the
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* tlb.
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*/
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if (first_cfg) {
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/* reserve a wired entry for pci config accesses */
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first_cfg = 0;
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pci_cfg_vm = get_vm_area(0x2000, 0);
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if (!pci_cfg_vm)
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panic (KERN_ERR "PCI unable to get vm area\n");
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pci_cfg_wired_entry = read_c0_wired();
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add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
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last_entryLo0 = last_entryLo1 = 0xffffffff;
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}
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/* Since the Au1xxx doesn't do the idsel timing exactly to spec,
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* many board vendors implement their own off-chip idsel, so call
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* it now. If it doesn't succeed, may as well bail out at this point.
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*/
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if (board_pci_idsel) {
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if (board_pci_idsel(device, 1) == 0) {
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*data = 0xffffffff;
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local_irq_restore(flags);
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return -1;
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}
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}
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/* setup the config window */
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if (bus->number == 0) {
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cfg_base = ((1<<device)<<11);
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} else {
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cfg_base = 0x80000000 | (bus->number<<16) | (device<<11);
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}
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/* setup the lower bits of the 36 bit address */
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offset = (function << 8) | (where & ~0x3);
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/* pick up any address that falls below the page mask */
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offset |= cfg_base & ~PAGE_MASK;
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/* page boundary */
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cfg_base = cfg_base & PAGE_MASK;
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entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
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entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
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if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
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mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
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(unsigned long)pci_cfg_vm->addr, PM_4K);
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last_entryLo0 = entryLo0;
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last_entryLo1 = entryLo1;
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}
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if (access_type == PCI_ACCESS_WRITE) {
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au_writel(*data, (int)(pci_cfg_vm->addr + offset));
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} else {
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*data = au_readl((int)(pci_cfg_vm->addr + offset));
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}
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au_sync_udelay(2);
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DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",
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access_type, bus->number, device, where, *data, offset);
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/* check master abort */
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status = au_readl(Au1500_PCI_STATCMD);
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if (status & (1<<29)) {
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*data = 0xffffffff;
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error = -1;
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DBG("Au1x Master Abort\n");
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} else if ((status >> 28) & 0xf) {
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DBG("PCI ERR detected: status %x\n", status);
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*data = 0xffffffff;
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error = -1;
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}
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/* Take away the idsel.
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*/
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if (board_pci_idsel) {
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(void)board_pci_idsel(device, 0);
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}
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local_irq_restore(flags);
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return error;
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#endif
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}
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static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
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int where, u8 * val)
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{
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u32 data;
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int ret;
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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*val = data & 0xff;
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return ret;
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}
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static int read_config_word(struct pci_bus *bus, unsigned int devfn,
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int where, u16 * val)
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{
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u32 data;
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int ret;
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
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if (where & 2)
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data >>= 16;
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*val = data & 0xffff;
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return ret;
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}
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static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, u32 * val)
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{
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int ret;
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
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return ret;
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}
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static int
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write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
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u8 val)
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{
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u32 data = 0;
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return -1;
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
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u16 val)
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{
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u32 data = 0;
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return -1;
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
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u32 val)
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{
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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static int config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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switch (size) {
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case 1: {
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u8 _val;
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int rc = read_config_byte(bus, devfn, where, &_val);
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*val = _val;
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return rc;
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}
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case 2: {
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u16 _val;
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int rc = read_config_word(bus, devfn, where, &_val);
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*val = _val;
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return rc;
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}
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default:
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return read_config_dword(bus, devfn, where, val);
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}
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}
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static int config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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switch (size) {
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case 1:
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return write_config_byte(bus, devfn, where, (u8) val);
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case 2:
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return write_config_word(bus, devfn, where, (u16) val);
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default:
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return write_config_dword(bus, devfn, where, val);
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}
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}
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struct pci_ops au1x_pci_ops = {
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config_read,
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config_write
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};
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