Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
This commit is contained in:
Linus Torvalds
222
arch/mips/vr41xx/common/bcu.c
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222
arch/mips/vr41xx/common/bcu.c
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/*
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* bcu.c, Bus Control Unit routines for the NEC VR4100 series.
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
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* Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
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* - New creation, NEC VR4122 and VR4131 are supported.
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* - Added support for NEC VR4111 and VR4121.
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*
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* Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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* - Added support for NEC VR4133.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#define CLKSPEEDREG_TYPE1 (void __iomem *)KSEG1ADDR(0x0b000014)
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#define CLKSPEEDREG_TYPE2 (void __iomem *)KSEG1ADDR(0x0f000014)
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#define CLKSP(x) ((x) & 0x001f)
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#define CLKSP_VR4133(x) ((x) & 0x0007)
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#define DIV2B 0x8000
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#define DIV3B 0x4000
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#define DIV4B 0x2000
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#define DIVT(x) (((x) & 0xf000) >> 12)
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#define DIVVT(x) (((x) & 0x0f00) >> 8)
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#define TDIVMODE(x) (2 << (((x) & 0x1000) >> 12))
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#define VTDIVMODE(x) (((x) & 0x0700) >> 8)
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static unsigned long vr41xx_vtclock;
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static unsigned long vr41xx_tclock;
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unsigned long vr41xx_get_vtclock_frequency(void)
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{
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return vr41xx_vtclock;
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}
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EXPORT_SYMBOL_GPL(vr41xx_get_vtclock_frequency);
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unsigned long vr41xx_get_tclock_frequency(void)
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{
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return vr41xx_tclock;
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}
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EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency);
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static inline uint16_t read_clkspeed(void)
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{
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1);
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case CPU_VR4122:
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case CPU_VR4131:
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case CPU_VR4133: return readw(CLKSPEEDREG_TYPE2);
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default:
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printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
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break;
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}
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return 0;
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}
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static inline unsigned long calculate_pclock(uint16_t clkspeed)
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{
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unsigned long pclock = 0;
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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case CPU_VR4121:
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pclock = 18432000 * 64;
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pclock /= CLKSP(clkspeed);
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break;
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case CPU_VR4122:
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pclock = 18432000 * 98;
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pclock /= CLKSP(clkspeed);
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break;
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case CPU_VR4131:
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pclock = 18432000 * 108;
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pclock /= CLKSP(clkspeed);
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break;
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case CPU_VR4133:
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switch (CLKSP_VR4133(clkspeed)) {
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case 0:
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pclock = 133000000;
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break;
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case 1:
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pclock = 149000000;
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break;
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case 2:
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pclock = 165900000;
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break;
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case 3:
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pclock = 199100000;
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break;
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case 4:
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pclock = 265900000;
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break;
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default:
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printk(KERN_INFO "Unknown PClock speed for NEC VR4133\n");
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break;
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}
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break;
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default:
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printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
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break;
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}
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printk(KERN_INFO "PClock: %ldHz\n", pclock);
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return pclock;
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}
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static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long pclock)
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{
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unsigned long vtclock = 0;
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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/* The NEC VR4111 doesn't have the VTClock. */
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break;
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case CPU_VR4121:
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vtclock = pclock;
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/* DIVVT == 9 Divide by 1.5 . VTClock = (PClock * 6) / 9 */
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if (DIVVT(clkspeed) == 9)
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vtclock = pclock * 6;
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/* DIVVT == 10 Divide by 2.5 . VTClock = (PClock * 4) / 10 */
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else if (DIVVT(clkspeed) == 10)
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vtclock = pclock * 4;
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vtclock /= DIVVT(clkspeed);
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printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
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break;
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case CPU_VR4122:
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if(VTDIVMODE(clkspeed) == 7)
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vtclock = pclock / 1;
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else if(VTDIVMODE(clkspeed) == 1)
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vtclock = pclock / 2;
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else
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vtclock = pclock / VTDIVMODE(clkspeed);
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printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
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break;
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case CPU_VR4131:
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case CPU_VR4133:
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vtclock = pclock / VTDIVMODE(clkspeed);
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printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
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break;
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default:
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printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
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break;
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}
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return vtclock;
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}
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static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pclock,
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unsigned long vtclock)
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{
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unsigned long tclock = 0;
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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if (!(clkspeed & DIV2B))
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tclock = pclock / 2;
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else if (!(clkspeed & DIV3B))
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tclock = pclock / 3;
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else if (!(clkspeed & DIV4B))
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tclock = pclock / 4;
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break;
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case CPU_VR4121:
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tclock = pclock / DIVT(clkspeed);
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break;
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case CPU_VR4122:
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case CPU_VR4131:
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case CPU_VR4133:
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tclock = vtclock / TDIVMODE(clkspeed);
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break;
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default:
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printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
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break;
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}
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printk(KERN_INFO "TClock: %ldHz\n", tclock);
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return tclock;
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}
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void vr41xx_calculate_clock_frequency(void)
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{
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unsigned long pclock;
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uint16_t clkspeed;
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clkspeed = read_clkspeed();
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pclock = calculate_pclock(clkspeed);
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vr41xx_vtclock = calculate_vtclock(clkspeed, pclock);
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vr41xx_tclock = calculate_tclock(clkspeed, pclock, vr41xx_vtclock);
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}
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EXPORT_SYMBOL_GPL(vr41xx_calculate_clock_frequency);
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