Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
This commit is contained in:
Linus Torvalds
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arch/sh/kernel/cpu/sh4/irq_intc2.c
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arch/sh/kernel/cpu/sh4/irq_intc2.c
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/*
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* linux/arch/sh/kernel/irq_intc2.c
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*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* Interrupt handling for INTC2-based IRQ.
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*
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* These are the "new Hitachi style" interrupts, as present on the
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* Hitachi 7751 and the STM ST40 STB1.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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struct intc2_data {
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unsigned char msk_offset;
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unsigned char msk_shift;
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#ifdef CONFIG_CPU_SUBTYPE_ST40
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int (*clear_irq) (int);
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#endif
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};
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static struct intc2_data intc2_data[NR_INTC2_IRQS];
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static void enable_intc2_irq(unsigned int irq);
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static void disable_intc2_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_intc2_irq disable_intc2_irq
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static void mask_and_ack_intc2(unsigned int);
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static void end_intc2_irq(unsigned int irq);
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static unsigned int startup_intc2_irq(unsigned int irq)
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{
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enable_intc2_irq(irq);
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return 0; /* never anything pending */
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}
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static struct hw_interrupt_type intc2_irq_type = {
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"INTC2-IRQ",
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startup_intc2_irq,
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shutdown_intc2_irq,
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enable_intc2_irq,
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disable_intc2_irq,
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mask_and_ack_intc2,
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end_intc2_irq
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};
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static void disable_intc2_irq(unsigned int irq)
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{
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int irq_offset = irq - INTC2_FIRST_IRQ;
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int msk_shift, msk_offset;
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// Sanity check
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if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
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return;
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msk_shift = intc2_data[irq_offset].msk_shift;
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msk_offset = intc2_data[irq_offset].msk_offset;
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ctrl_outl(1<<msk_shift,
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INTC2_BASE+INTC2_INTMSK_OFFSET+msk_offset);
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}
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static void enable_intc2_irq(unsigned int irq)
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{
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int irq_offset = irq - INTC2_FIRST_IRQ;
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int msk_shift, msk_offset;
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/* Sanity check */
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if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
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return;
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msk_shift = intc2_data[irq_offset].msk_shift;
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msk_offset = intc2_data[irq_offset].msk_offset;
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ctrl_outl(1<<msk_shift,
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INTC2_BASE+INTC2_INTMSKCLR_OFFSET+msk_offset);
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}
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static void mask_and_ack_intc2(unsigned int irq)
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{
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disable_intc2_irq(irq);
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}
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static void end_intc2_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_intc2_irq(irq);
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#ifdef CONFIG_CPU_SUBTYPE_ST40
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if (intc2_data[irq - INTC2_FIRST_IRQ].clear_irq)
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intc2_data[irq - INTC2_FIRST_IRQ].clear_irq (irq);
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#endif
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}
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/*
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* Setup an INTC2 style interrupt.
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* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
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* allowing the use of the numbers straight out of the datasheet.
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* For example:
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* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
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* would be: ^ ^ ^ ^
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* | | | |
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* make_intc2_irq(84, 0, 16, 0, 13);
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*/
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void make_intc2_irq(unsigned int irq,
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unsigned int ipr_offset, unsigned int ipr_shift,
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unsigned int msk_offset, unsigned int msk_shift,
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unsigned int priority)
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{
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int irq_offset = irq - INTC2_FIRST_IRQ;
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unsigned int flags;
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unsigned long ipr;
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if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
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return;
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disable_irq_nosync(irq);
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/* Fill the data we need */
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intc2_data[irq_offset].msk_offset = msk_offset;
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intc2_data[irq_offset].msk_shift = msk_shift;
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#ifdef CONFIG_CPU_SUBTYPE_ST40
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intc2_data[irq_offset].clear_irq = NULL;
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#endif
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/* Set the priority level */
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local_irq_save(flags);
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ipr=ctrl_inl(INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset);
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ipr&=~(0xf<<ipr_shift);
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ipr|=(priority)<<ipr_shift;
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ctrl_outl(ipr, INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset);
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local_irq_restore(flags);
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irq_desc[irq].handler=&intc2_irq_type;
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disable_intc2_irq(irq);
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}
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#ifdef CONFIG_CPU_SUBTYPE_ST40
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struct intc2_init {
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unsigned short irq;
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unsigned char ipr_offset, ipr_shift;
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unsigned char msk_offset, msk_shift;
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};
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static struct intc2_init intc2_init_data[] __initdata = {
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{64, 0, 0, 0, 0}, /* PCI serr */
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{65, 0, 4, 0, 1}, /* PCI err */
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{66, 0, 4, 0, 2}, /* PCI ad */
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{67, 0, 4, 0, 3}, /* PCI pwd down */
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{72, 0, 8, 0, 5}, /* DMAC INT0 */
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{73, 0, 8, 0, 6}, /* DMAC INT1 */
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{74, 0, 8, 0, 7}, /* DMAC INT2 */
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{75, 0, 8, 0, 8}, /* DMAC INT3 */
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{76, 0, 8, 0, 9}, /* DMAC INT4 */
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{78, 0, 8, 0, 11}, /* DMAC ERR */
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{80, 0, 12, 0, 12}, /* PIO0 */
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{84, 0, 16, 0, 13}, /* PIO1 */
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{88, 0, 20, 0, 14}, /* PIO2 */
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{112, 4, 0, 4, 0}, /* Mailbox */
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#ifdef CONFIG_CPU_SUBTYPE_ST40GX1
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{116, 4, 4, 4, 4}, /* SSC0 */
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{120, 4, 8, 4, 8}, /* IR Blaster */
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{124, 4, 12, 4, 12}, /* USB host */
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{128, 4, 16, 4, 16}, /* Video processor BLITTER */
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{132, 4, 20, 4, 20}, /* UART0 */
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{134, 4, 20, 4, 22}, /* UART2 */
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{136, 4, 24, 4, 24}, /* IO_PIO0 */
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{140, 4, 28, 4, 28}, /* EMPI */
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{144, 8, 0, 8, 0}, /* MAFE */
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{148, 8, 4, 8, 4}, /* PWM */
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{152, 8, 8, 8, 8}, /* SSC1 */
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{156, 8, 12, 8, 12}, /* IO_PIO1 */
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{160, 8, 16, 8, 16}, /* USB target */
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{164, 8, 20, 8, 20}, /* UART1 */
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{168, 8, 24, 8, 24}, /* Teletext */
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{172, 8, 28, 8, 28}, /* VideoSync VTG */
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{173, 8, 28, 8, 29}, /* VideoSync DVP0 */
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{174, 8, 28, 8, 30}, /* VideoSync DVP1 */
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#endif
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};
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void __init init_IRQ_intc2(void)
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{
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struct intc2_init *p;
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printk(KERN_ALERT "init_IRQ_intc2\n");
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for (p = intc2_init_data;
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p<intc2_init_data+ARRAY_SIZE(intc2_init_data);
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p++) {
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make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
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p-> msk_offset, p->msk_shift, 13);
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}
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}
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/* Adds a termination callback to the interrupt */
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void intc2_add_clear_irq(int irq, int (*fn)(int))
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{
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if (irq < INTC2_FIRST_IRQ)
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return;
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intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
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}
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#endif /* CONFIG_CPU_SUBTYPE_ST40 */
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