Blackfin arch: Functional power management support
Enable: PM_SUSPEND_MEM -> Blackfin Hibernate to SDRAM This feature requires a special bootloader (u-boot) supporting return from hibernate. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
committed by
Bryan Wu
Bryan Wu
parent
4f13f548ce
commit
1efc80b53e
@@ -38,8 +38,9 @@
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/dpmc.h>
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#include <asm/gpio.h>
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#include <asm/dma.h>
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#include <asm/dpmc.h>
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#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
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#define WAKEUP_TYPE PM_WAKE_HIGH
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@@ -61,16 +62,17 @@
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#define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
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#endif
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void bfin_pm_suspend_standby_enter(void)
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{
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unsigned long flags;
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#ifdef CONFIG_PM_WAKEUP_BY_GPIO
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gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
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#endif
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u32 flags;
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local_irq_save(flags);
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bfin_pm_setup();
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bfin_pm_standby_setup();
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#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
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sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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@@ -78,7 +80,7 @@ void bfin_pm_suspend_standby_enter(void)
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sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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#endif
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bfin_pm_restore();
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bfin_pm_standby_restore();
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
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bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
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@@ -93,6 +95,195 @@ void bfin_pm_suspend_standby_enter(void)
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local_irq_restore(flags);
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}
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int bf53x_suspend_l1_mem(unsigned char *memptr)
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{
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dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
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dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
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L1_DATA_A_LENGTH);
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dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
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(const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
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memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
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L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
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L1_SCRATCH_LENGTH);
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return 0;
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}
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int bf53x_resume_l1_mem(unsigned char *memptr)
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{
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dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
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dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
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L1_DATA_A_LENGTH);
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dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
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L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
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memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
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L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
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return 0;
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}
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#ifdef CONFIG_BFIN_WB
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static void flushinv_all_dcache(void)
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{
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u32 way, bank, subbank, set;
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u32 status, addr;
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u32 dmem_ctl = bfin_read_DMEM_CONTROL();
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for (bank = 0; bank < 2; ++bank) {
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if (!(dmem_ctl & (1 << (DMC1_P - bank))))
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continue;
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for (way = 0; way < 2; ++way)
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for (subbank = 0; subbank < 4; ++subbank)
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for (set = 0; set < 64; ++set) {
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bfin_write_DTEST_COMMAND(
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way << 26 |
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bank << 23 |
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subbank << 16 |
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set << 5
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);
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CSYNC();
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status = bfin_read_DTEST_DATA0();
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/* only worry about valid/dirty entries */
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if ((status & 0x3) != 0x3)
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continue;
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/* construct the address using the tag */
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addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
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/* flush it */
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__asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
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}
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}
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}
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#endif
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static inline void dcache_disable(void)
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{
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#ifdef CONFIG_BFIN_DCACHE
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unsigned long ctrl;
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#ifdef CONFIG_BFIN_WB
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flushinv_all_dcache();
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#endif
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SSYNC();
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ctrl = bfin_read_DMEM_CONTROL();
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ctrl &= ~ENDCPLB;
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bfin_write_DMEM_CONTROL(ctrl);
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SSYNC();
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#endif
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}
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static inline void dcache_enable(void)
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{
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#ifdef CONFIG_BFIN_DCACHE
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unsigned long ctrl;
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SSYNC();
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ctrl = bfin_read_DMEM_CONTROL();
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ctrl |= ENDCPLB;
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bfin_write_DMEM_CONTROL(ctrl);
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SSYNC();
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#endif
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}
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static inline void icache_disable(void)
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{
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#ifdef CONFIG_BFIN_ICACHE
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unsigned long ctrl;
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SSYNC();
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ctrl = bfin_read_IMEM_CONTROL();
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ctrl &= ~ENICPLB;
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bfin_write_IMEM_CONTROL(ctrl);
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SSYNC();
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#endif
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}
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static inline void icache_enable(void)
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{
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#ifdef CONFIG_BFIN_ICACHE
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unsigned long ctrl;
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SSYNC();
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ctrl = bfin_read_IMEM_CONTROL();
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ctrl |= ENICPLB;
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bfin_write_IMEM_CONTROL(ctrl);
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SSYNC();
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#endif
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}
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int bfin_pm_suspend_mem_enter(void)
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{
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unsigned long flags;
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int wakeup, ret;
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unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
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+ L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
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GFP_KERNEL);
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if (memptr == NULL) {
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panic("bf53x_suspend_l1_mem malloc failed");
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return -ENOMEM;
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}
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wakeup = bfin_read_VR_CTL() & ~FREQ;
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wakeup |= SCKELOW;
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/* FIXME: merge this somehow with set_irq_wake */
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#ifdef CONFIG_PM_BFIN_WAKE_RTC
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wakeup |= WAKE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PH6
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wakeup |= PHYWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_CAN
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wakeup |= CANWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_GP
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wakeup |= GPWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_USB
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wakeup |= USBWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_KEYPAD
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wakeup |= KPADWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_ROTARY
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wakeup |= ROTWE;
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#endif
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local_irq_save(flags);
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ret = blackfin_dma_suspend();
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if (ret) {
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local_irq_restore(flags);
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kfree(memptr);
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return ret;
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}
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bfin_gpio_pm_hibernate_suspend();
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dcache_disable();
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icache_disable();
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bf53x_suspend_l1_mem(memptr);
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do_hibernate(wakeup); /* Goodbye */
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bf53x_resume_l1_mem(memptr);
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icache_enable();
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dcache_enable();
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bfin_gpio_pm_hibernate_restore();
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blackfin_dma_resume();
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local_irq_restore(flags);
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kfree(memptr);
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return 0;
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}
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/*
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* bfin_pm_valid - Tell the PM core that we only support the standby sleep
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* state
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@@ -101,7 +292,24 @@ void bfin_pm_suspend_standby_enter(void)
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*/
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static int bfin_pm_valid(suspend_state_t state)
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{
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return (state == PM_SUSPEND_STANDBY);
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return (state == PM_SUSPEND_STANDBY
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#ifndef BF533_FAMILY
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/*
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* On BF533/2/1:
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* If we enter Hibernate the SCKE Pin is driven Low,
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* so that the SDRAM enters Self Refresh Mode.
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* However when the reset sequence that follows hibernate
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* state is executed, SCKE is driven High, taking the
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* SDRAM out of Self Refresh.
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*
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* If you reconfigure and access the SDRAM "very quickly",
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* you are likely to avoid errors, otherwise the SDRAM
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* start losing its contents.
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* An external HW workaround is possible using logic gates.
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*/
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|| state == PM_SUSPEND_MEM
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#endif
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);
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}
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/*
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@@ -115,10 +323,9 @@ static int bfin_pm_enter(suspend_state_t state)
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case PM_SUSPEND_STANDBY:
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bfin_pm_suspend_standby_enter();
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break;
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case PM_SUSPEND_MEM:
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return -ENOTSUPP;
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bfin_pm_suspend_mem_enter();
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break;
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default:
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return -EINVAL;
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}
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