Blackfin: add support for gptimer0 as a tick source
For systems where the core cycles are not a usable tick source (like SMP or cycles gets updated), enable gptimer0 as an alternative. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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committed by
Mike Frysinger
parent
555487bbb6
commit
1fa9be72b5
@@ -1052,7 +1052,7 @@ int __init init_arch_irq(void)
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set_irq_chained_handler(irq, bfin_demux_error_irq);
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break;
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#endif
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#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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case IRQ_TIMER0:
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set_irq_handler(irq, handle_percpu_irq);
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break;
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@@ -1232,13 +1232,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
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if (likely(vec == EVT_IVTMR_P)) {
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irq = IRQ_CORETMR;
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goto core_tick;
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}
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SSYNC();
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} else {
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
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{
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unsigned long sic_status[3];
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sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
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@@ -1254,9 +1250,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
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if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
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break;
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}
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}
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#else
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{
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unsigned long sic_status;
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sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
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@@ -1268,15 +1262,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
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} else if (sic_status & ivg->isrflag)
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break;
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}
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}
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#endif
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irq = ivg->irqno;
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irq = ivg->irqno;
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}
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if (irq == IRQ_SYSTMR) {
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#ifdef CONFIG_GENERIC_CLOCKEVENTS
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core_tick:
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#else
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#ifndef CONFIG_GENERIC_CLOCKEVENTS
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bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
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#endif
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/* This is basically what we need from the register frame. */
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@@ -1288,9 +1280,6 @@ core_tick:
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__raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
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}
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#ifndef CONFIG_GENERIC_CLOCKEVENTS
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core_tick:
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#endif
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if (this_domain == ipipe_root_domain) {
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s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
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barrier();
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@@ -1308,7 +1297,7 @@ core_tick:
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}
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}
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return 0;
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return 0;
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}
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#endif /* CONFIG_IPIPE */
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