lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

x86: Coding style fixes to arch/x86/oprofile/op_model_p4.c

Browse Source 
A coding style patch to arch/x86/oprofile/op_model_p4.c that
removes 87 errors and 4 warnings.

Before:
total: 89 errors, 13 warnings, 722 lines checked

After:
total: 2 errors, 9 warnings, 721 lines checked

Compile tested, binary verified as follow:

paolo@paolo-desktop:~/linux.trees.git$ size /tmp/op_model_p4.o.*
   text    data     bss     dec     hex filename
   2691     968      32    3691     e6b /tmp/op_model_p4.o.after
   2691     968      32    3691     e6b /tmp/op_model_p4.o.before

paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/op_model_p4.o.*
8c1c9823bab33333e1f7f76574e62561  /tmp/op_model_p4.o.after
8c1c9823bab33333e1f7f76574e62561  /tmp/op_model_p4.o.before

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Cc: robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi
2008-08-18 21:25:38 +02:00
committed by Ingo Molnar
parent a7f5aaf36d
commit 20211e4d34
1 changed files with 87 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
arch/x86/oprofile/op_model_p4.c
View File

@@ -10,11 +10,12 @@
#include <linux/oprofile.h> #include <linux/oprofile.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <linux/ptrace.h>
#include <linux/nmi.h>
#include <asm/msr.h> #include <asm/msr.h>
#include <asm/ptrace.h>
#include <asm/fixmap.h> #include <asm/fixmap.h>
#include <asm/apic.h> #include <asm/apic.h>
#include <asm/nmi.h>
#include "op_x86_model.h" #include "op_x86_model.h"
#include "op_counter.h" #include "op_counter.h"
@@ -40,7 +41,7 @@ static unsigned int num_controls = NUM_CONTROLS_NON_HT;
static inline void setup_num_counters(void) static inline void setup_num_counters(void)
{ {
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
if (smp_num_siblings == 2){ if (smp_num_siblings == 2) {
num_counters = NUM_COUNTERS_HT2; num_counters = NUM_COUNTERS_HT2;
num_controls = NUM_CONTROLS_HT2; num_controls = NUM_CONTROLS_HT2;
} }
@@ -86,7 +87,7 @@ struct p4_event_binding {
#define CTR_FLAME_2 (1 << 6) #define CTR_FLAME_2 (1 << 6)
#define CTR_IQ_5 (1 << 7) #define CTR_IQ_5 (1 << 7)
static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = { static struct p4_counter_binding p4_counters[NUM_COUNTERS_NON_HT] = {
{ CTR_BPU_0, MSR_P4_BPU_PERFCTR0, MSR_P4_BPU_CCCR0 }, { CTR_BPU_0, MSR_P4_BPU_PERFCTR0, MSR_P4_BPU_CCCR0 },
{ CTR_MS_0, MSR_P4_MS_PERFCTR0, MSR_P4_MS_CCCR0 }, { CTR_MS_0, MSR_P4_MS_PERFCTR0, MSR_P4_MS_CCCR0 },
{ CTR_FLAME_0, MSR_P4_FLAME_PERFCTR0, MSR_P4_FLAME_CCCR0 }, { CTR_FLAME_0, MSR_P4_FLAME_PERFCTR0, MSR_P4_FLAME_CCCR0 },
@@ -97,7 +98,7 @@ static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = {
{ CTR_IQ_5, MSR_P4_IQ_PERFCTR5, MSR_P4_IQ_CCCR5 } { CTR_IQ_5, MSR_P4_IQ_PERFCTR5, MSR_P4_IQ_CCCR5 }
}; };
#define NUM_UNUSED_CCCRS NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT #define NUM_UNUSED_CCCRS (NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT)
/* p4 event codes in libop/op_event.h are indices into this table. */ /* p4 event codes in libop/op_event.h are indices into this table. */
@@ -349,8 +350,8 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
#define ESCR_SET_OS_1(escr, os) ((escr) |= (((os) & 1) << 1)) #define ESCR_SET_OS_1(escr, os) ((escr) |= (((os) & 1) << 1))
#define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25)) #define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25))
#define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9)) #define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9))
#define ESCR_READ(escr,high,ev,i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0) #define ESCR_READ(escr, high, ev, i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
#define ESCR_WRITE(escr,high,ev,i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0) #define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
#define CCCR_RESERVED_BITS 0x38030FFF #define CCCR_RESERVED_BITS 0x38030FFF
#define CCCR_CLEAR(cccr) ((cccr) &= CCCR_RESERVED_BITS) #define CCCR_CLEAR(cccr) ((cccr) &= CCCR_RESERVED_BITS)
@@ -360,15 +361,15 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
#define CCCR_SET_PMI_OVF_1(cccr) ((cccr) |= (1<<27)) #define CCCR_SET_PMI_OVF_1(cccr) ((cccr) |= (1<<27))
#define CCCR_SET_ENABLE(cccr) ((cccr) |= (1<<12)) #define CCCR_SET_ENABLE(cccr) ((cccr) |= (1<<12))
#define CCCR_SET_DISABLE(cccr) ((cccr) &= ~(1<<12)) #define CCCR_SET_DISABLE(cccr) ((cccr) &= ~(1<<12))
#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0) #define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0) #define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
#define CCCR_OVF_P(cccr) ((cccr) & (1U<<31)) #define CCCR_OVF_P(cccr) ((cccr) & (1U<<31))
#define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31))) #define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31)))
#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0) #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0) #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
#define CTR_READ(l,h,i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h));} while (0) #define CTR_READ(l, h, i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h)); } while (0)
#define CTR_WRITE(l,i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0) #define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1); } while (0)
#define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000)) #define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000))
@@ -402,18 +403,16 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
stag = get_stagger(); stag = get_stagger();
/* initialize some registers */ /* initialize some registers */
for (i = 0; i < num_counters; ++i) { for (i = 0; i < num_counters; ++i)
msrs->counters[i].addr = 0; msrs->counters[i].addr = 0;
} for (i = 0; i < num_controls; ++i)
for (i = 0; i < num_controls; ++i) {
msrs->controls[i].addr = 0; msrs->controls[i].addr = 0;
}
/* the counter & cccr registers we pay attention to */ /* the counter & cccr registers we pay attention to */
for (i = 0; i < num_counters; ++i) { for (i = 0; i < num_counters; ++i) {
addr = p4_counters[VIRT_CTR(stag, i)].counter_address; addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
cccraddr = p4_counters[VIRT_CTR(stag, i)].cccr_address; cccraddr = p4_counters[VIRT_CTR(stag, i)].cccr_address;
if (reserve_perfctr_nmi(addr)){ if (reserve_perfctr_nmi(addr)) {
msrs->counters[i].addr = addr; msrs->counters[i].addr = addr;
msrs->controls[i].addr = cccraddr; msrs->controls[i].addr = cccraddr;
} }
@@ -534,11 +533,10 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
CCCR_CLEAR(cccr); CCCR_CLEAR(cccr);
CCCR_SET_REQUIRED_BITS(cccr); CCCR_SET_REQUIRED_BITS(cccr);
CCCR_SET_ESCR_SELECT(cccr, ev->escr_select); CCCR_SET_ESCR_SELECT(cccr, ev->escr_select);
if (stag == 0) { if (stag == 0)
CCCR_SET_PMI_OVF_0(cccr); CCCR_SET_PMI_OVF_0(cccr);
} else { else
CCCR_SET_PMI_OVF_1(cccr); CCCR_SET_PMI_OVF_1(cccr);
}
CCCR_WRITE(cccr, high, VIRT_CTR(stag, ctr)); CCCR_WRITE(cccr, high, VIRT_CTR(stag, ctr));
return; return;
} }
@@ -559,14 +557,14 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
stag = get_stagger(); stag = get_stagger();
rdmsr(MSR_IA32_MISC_ENABLE, low, high); rdmsr(MSR_IA32_MISC_ENABLE, low, high);
if (! MISC_PMC_ENABLED_P(low)) { if (!MISC_PMC_ENABLED_P(low)) {
printk(KERN_ERR "oprofile: P4 PMC not available\n"); printk(KERN_ERR "oprofile: P4 PMC not available\n");
return; return;
} }
/* clear the cccrs we will use */ /* clear the cccrs we will use */
for (i = 0 ; i < num_counters ; i++) { for (i = 0 ; i < num_counters ; i++) {
if (unlikely(!CTRL_IS_RESERVED(msrs,i))) if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
continue; continue;
rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
CCCR_CLEAR(low); CCCR_CLEAR(low);
@@ -576,14 +574,14 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
/* clear all escrs (including those outside our concern) */ /* clear all escrs (including those outside our concern) */
for (i = num_counters; i < num_controls; i++) { for (i = num_counters; i < num_controls; i++) {
if (unlikely(!CTRL_IS_RESERVED(msrs,i))) if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
continue; continue;
wrmsr(msrs->controls[i].addr, 0, 0); wrmsr(msrs->controls[i].addr, 0, 0);
} }
/* setup all counters */ /* setup all counters */
for (i = 0 ; i < num_counters ; ++i) { for (i = 0 ; i < num_counters ; ++i) {
if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs,i))) { if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs, i))) {
reset_value[i] = counter_config[i].count; reset_value[i] = counter_config[i].count;
pmc_setup_one_p4_counter(i); pmc_setup_one_p4_counter(i);
CTR_WRITE(counter_config[i].count, VIRT_CTR(stag, i)); CTR_WRITE(counter_config[i].count, VIRT_CTR(stag, i));
@@ -627,13 +625,13 @@ static int p4_check_ctrs(struct pt_regs * const regs,
real = VIRT_CTR(stag, i); real = VIRT_CTR(stag, i);
CCCR_READ(low, high, real); CCCR_READ(low, high, real);
CTR_READ(ctr, high, real); CTR_READ(ctr, high, real);
if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) { if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
oprofile_add_sample(regs, i); oprofile_add_sample(regs, i);
CTR_WRITE(reset_value[i], real); CTR_WRITE(reset_value[i], real);
CCCR_CLEAR_OVF(low); CCCR_CLEAR_OVF(low);
CCCR_WRITE(low, high, real); CCCR_WRITE(low, high, real);
CTR_WRITE(reset_value[i], real); CTR_WRITE(reset_value[i], real);
} }
} }
@@ -683,15 +681,16 @@ static void p4_shutdown(struct op_msrs const * const msrs)
int i; int i;
for (i = 0 ; i < num_counters ; ++i) { for (i = 0 ; i < num_counters ; ++i) {
if (CTR_IS_RESERVED(msrs,i)) if (CTR_IS_RESERVED(msrs, i))
release_perfctr_nmi(msrs->counters[i].addr); release_perfctr_nmi(msrs->counters[i].addr);
} }
/* some of the control registers are specially reserved in /*
* some of the control registers are specially reserved in
* conjunction with the counter registers (hence the starting offset). * conjunction with the counter registers (hence the starting offset).
* This saves a few bits. * This saves a few bits.
*/ */
for (i = num_counters ; i < num_controls ; ++i) { for (i = num_counters ; i < num_controls ; ++i) {
if (CTRL_IS_RESERVED(msrs,i)) if (CTRL_IS_RESERVED(msrs, i))
release_evntsel_nmi(msrs->controls[i].addr); release_evntsel_nmi(msrs->controls[i].addr);
} }
} }