[SCSI] mpt2sas: MPI header version N is updated.
Updating MPI header version N. Removed mpi_history.txt. Signed-off-by: Kashyap Desai <kashyap.desai@lsi.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
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Kashyap, Desai
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James Bottomley
James Bottomley
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d32a8c15e1
commit
203d65b16c
@ -6,7 +6,7 @@
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* Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
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* Creation Date: October 11, 2006
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*
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* mpi2_ioc.h Version: 02.00.13
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* mpi2_ioc.h Version: 02.00.14
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*
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* Version History
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* ---------------
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@ -98,6 +98,9 @@
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* (MPI2_FW_HEADER_PID_).
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* Modified values for SAS ProductID Family
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* (MPI2_FW_HEADER_PID_FAMILY_).
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* 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
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* Added PowerManagementControl Request structures and
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* defines.
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* --------------------------------------------------------------------------
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*/
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@ -469,6 +472,7 @@ typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
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#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
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#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
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#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
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#define MPI2_EVENT_SAS_QUIESCE (0x0025)
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/* Log Entry Added Event data */
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@ -895,6 +899,22 @@ typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
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* */
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/* SAS Quiesce Event data */
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typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
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U8 ReasonCode; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U16 Reserved2; /* 0x02 */
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U32 Reserved3; /* 0x04 */
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} MPI2_EVENT_DATA_SAS_QUIESCE,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
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Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
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/* SAS Quiesce Event data ReasonCode values */
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#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
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#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
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/* Host Based Discovery Phy Event data */
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typedef struct _MPI2_EVENT_HBD_PHY_SAS {
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@ -1006,6 +1026,7 @@ typedef struct _MPI2_FW_DOWNLOAD_REQUEST
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#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
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#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
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#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
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#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
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#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
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/* FWDownload TransactionContext Element */
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@ -1183,7 +1204,6 @@ typedef struct _MPI2_FW_IMAGE_HEADER
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#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
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#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
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#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
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#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
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#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
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@ -1407,5 +1427,100 @@ typedef struct _MPI2_INIT_IMAGE_FOOTER
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#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
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/****************************************************************************
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* PowerManagementControl message
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****************************************************************************/
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/* PowerManagementControl Request message */
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typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
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U8 Feature; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U8 Parameter1; /* 0x0C */
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U8 Parameter2; /* 0x0D */
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U8 Parameter3; /* 0x0E */
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U8 Parameter4; /* 0x0F */
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U32 Reserved5; /* 0x10 */
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U32 Reserved6; /* 0x14 */
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} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
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Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
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/* defines for the Feature field */
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#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
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#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
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#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03)
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#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
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#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
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#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
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/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
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/* Parameter1 contains a PHY number */
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/* Parameter2 indicates power condition action using these defines */
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#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
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#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
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#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
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/* Parameter3 and Parameter4 are reserved */
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/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
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* Feature */
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/* Parameter1 contains SAS port width modulation group number */
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/* Parameter2 indicates IOC action using these defines */
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#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
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#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
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#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
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/* Parameter3 indicates desired modulation level using these defines */
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#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
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#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
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#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
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#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
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/* Parameter4 is reserved */
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/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
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/* Parameter1 indicates desired PCIe link speed using these defines */
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#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00)
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#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01)
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#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02)
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/* Parameter2 indicates desired PCIe link width using these defines */
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#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01)
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#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02)
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#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04)
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#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08)
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/* Parameter3 and Parameter4 are reserved */
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/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
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/* Parameter1 indicates desired IOC hardware clock speed using these defines */
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#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
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#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
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#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
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#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
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/* Parameter2, Parameter3, and Parameter4 are reserved */
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/* PowerManagementControl Reply message */
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typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
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U8 Feature; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Reserved5; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
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Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
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#endif
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