drm/radeon/kms: Convert R300 to new init path
Also cleanup register specific to R300. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Jerome Glisse
committed by
Dave Airlie
Dave Airlie
parent
ca6ffc64cb
commit
207bf9e90c
@@ -34,42 +34,15 @@
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#include "r100_track.h"
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#include "r300d.h"
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#include "rv350d.h"
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#include "r300_reg_safe.h"
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/* r300,r350,rv350,rv370,rv380 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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int r100_cp_reset(struct radeon_device *rdev);
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int r100_rb2d_reset(struct radeon_device *rdev);
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int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
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int r100_pci_gart_enable(struct radeon_device *rdev);
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void r100_mc_setup(struct radeon_device *rdev);
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void r100_mc_disable_clients(struct radeon_device *rdev);
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int r100_gui_wait_for_idle(struct radeon_device *rdev);
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int r100_cs_packet_parse(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx);
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int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
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int r100_cs_parse_packet0(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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const unsigned *auth, unsigned n,
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radeon_packet0_check_t check);
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int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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struct radeon_object *robj);
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/* This files gather functions specifics to:
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* r300,r350,rv350,rv370,rv380
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void r300_gpu_init(struct radeon_device *rdev);
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int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
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/*
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* rv370,rv380 PCIE GART
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*/
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static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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@@ -182,59 +155,6 @@ void rv370_pcie_gart_fini(struct radeon_device *rdev)
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radeon_gart_fini(rdev);
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}
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/*
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* MC
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*/
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int r300_mc_init(struct radeon_device *rdev)
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{
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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r300_gpu_init(rdev);
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r100_pci_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCIE) {
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rv370_pcie_gart_disable(rdev);
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}
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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printk(KERN_WARNING "[drm] Disabling AGP\n");
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rdev->flags &= ~RADEON_IS_AGP;
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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} else {
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rdev->mc.gtt_location = rdev->mc.agp_base;
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}
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}
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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r100_mc_disable_clients(rdev);
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if (r300_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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r100_mc_setup(rdev);
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return 0;
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}
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void r300_mc_fini(struct radeon_device *rdev)
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{
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}
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/*
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* Fence emission
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*/
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void r300_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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@@ -260,10 +180,6 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
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}
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/*
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* Global GPU functions
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*/
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int r300_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset,
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uint64_t dst_offset,
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@@ -582,11 +498,6 @@ void r300_vram_info(struct radeon_device *rdev)
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r100_vram_init_sizes(rdev);
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}
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/*
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* PCIE Lanes
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*/
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void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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{
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uint32_t link_width_cntl, mask;
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@@ -646,10 +557,6 @@ void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
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{
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@@ -680,7 +587,7 @@ static struct drm_info_list rv370_pcie_gart_info_list[] = {
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};
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#endif
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int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
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@@ -689,10 +596,6 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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#endif
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}
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/*
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* CS functions
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*/
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static int r300_packet0_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg)
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@@ -1226,12 +1129,6 @@ void r300_set_reg_safe(struct radeon_device *rdev)
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
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}
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int r300_init(struct radeon_device *rdev)
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{
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r300_set_reg_safe(rdev);
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return 0;
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}
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void r300_mc_program(struct radeon_device *rdev)
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{
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struct r100_mc_save save;
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@@ -1279,3 +1176,185 @@ void r300_clock_startup(struct radeon_device *rdev)
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tmp |= S_00000D_FORCE_VAP(1);
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WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
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}
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static int r300_startup(struct radeon_device *rdev)
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{
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int r;
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r300_mc_program(rdev);
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/* Resume clock */
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r300_clock_startup(rdev);
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/* Initialize GPU configuration (# pipes, ...) */
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r300_gpu_init(rdev);
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/* Initialize GART (initialize after TTM so we can allocate
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* memory through TTM but finalize after TTM) */
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_enable(rdev);
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if (r)
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return r;
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}
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if (rdev->flags & RADEON_IS_PCI) {
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r = r100_pci_gart_enable(rdev);
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if (r)
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return r;
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}
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/* Enable IRQ */
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rdev->irq.sw_int = true;
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r100_irq_set(rdev);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
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return r;
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}
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r = r100_wb_init(rdev);
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if (r)
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dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
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r = r100_ib_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
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return r;
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}
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return 0;
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}
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int r300_resume(struct radeon_device *rdev)
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{
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/* Make sur GART are not working */
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_disable(rdev);
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/* Resume clock before doing reset */
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r300_clock_startup(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* post */
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radeon_combios_asic_init(rdev->ddev);
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/* Resume clock after posting */
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r300_clock_startup(rdev);
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return r300_startup(rdev);
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}
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int r300_suspend(struct radeon_device *rdev)
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{
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r100_cp_disable(rdev);
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r100_wb_disable(rdev);
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r100_irq_disable(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_disable(rdev);
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return 0;
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}
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void r300_fini(struct radeon_device *rdev)
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{
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r300_suspend(rdev);
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r100_cp_fini(rdev);
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r100_wb_fini(rdev);
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r100_ib_fini(rdev);
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radeon_gem_fini(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_fini(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_fini(rdev);
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radeon_irq_kms_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_object_fini(rdev);
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radeon_atombios_fini(rdev);
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kfree(rdev->bios);
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rdev->bios = NULL;
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}
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int r300_init(struct radeon_device *rdev)
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{
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int r;
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rdev->new_init_path = true;
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/* Disable VGA */
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r100_vga_render_disable(rdev);
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/* Initialize scratch registers */
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radeon_scratch_init(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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/* TODO: disable VGA need to use VGA request */
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/* BIOS*/
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if (!radeon_get_bios(rdev)) {
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if (ASIC_IS_AVIVO(rdev))
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return -EINVAL;
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}
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if (rdev->is_atom_bios) {
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dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
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return -EINVAL;
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} else {
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r = radeon_combios_init(rdev);
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if (r)
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return r;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* check if cards are posted or not */
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if (!radeon_card_posted(rdev) && rdev->bios) {
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DRM_INFO("GPU not posted. posting now...\n");
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radeon_combios_asic_init(rdev->ddev);
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}
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/* Set asic errata */
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r300_errata(rdev);
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/* Initialize clocks */
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radeon_get_clock_info(rdev->ddev);
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/* Get vram informations */
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r300_vram_info(rdev);
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/* Initialize memory controller (also test AGP) */
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r = r420_mc_init(rdev);
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if (r)
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return r;
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/* Fence driver */
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r = radeon_fence_driver_init(rdev);
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if (r)
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return r;
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r = radeon_irq_kms_init(rdev);
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if (r)
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return r;
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/* Memory manager */
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r = radeon_object_init(rdev);
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if (r)
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return r;
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_init(rdev);
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if (r)
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return r;
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}
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if (rdev->flags & RADEON_IS_PCI) {
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r = r100_pci_gart_init(rdev);
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if (r)
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return r;
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}
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r300_set_reg_safe(rdev);
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rdev->accel_working = true;
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r = r300_startup(rdev);
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if (r) {
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/* Somethings want wront with the accel init stop accel */
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dev_err(rdev->dev, "Disabling GPU acceleration\n");
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r300_suspend(rdev);
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r100_cp_fini(rdev);
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r100_wb_fini(rdev);
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r100_ib_fini(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_fini(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_fini(rdev);
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radeon_irq_kms_fini(rdev);
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rdev->accel_working = false;
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}
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return 0;
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}
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