ath5k: no need to save/restore the default antenna
Since ath5k_hw_set_antenna_mode() always writes the default antenna register and is called at the end of reset, there is no need to separately save and restore the default antenna. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville
parent
0ca74027ac
commit
20fbed21e9
@@ -877,12 +877,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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struct ieee80211_channel *channel, bool change_channel)
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struct ieee80211_channel *channel, bool change_channel)
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{
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{
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struct ath_common *common = ath5k_hw_common(ah);
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struct ath_common *common = ath5k_hw_common(ah);
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u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo;
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u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
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u32 phy_tst1;
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u32 phy_tst1;
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u8 mode, freq, ee_mode;
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u8 mode, freq, ee_mode;
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int i, ret;
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int i, ret;
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s_ant = 0;
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ee_mode = 0;
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ee_mode = 0;
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staid1_flags = 0;
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staid1_flags = 0;
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tsf_up = 0;
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tsf_up = 0;
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@@ -979,9 +978,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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}
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}
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}
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}
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/* Save default antenna */
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s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
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if (ah->ah_version == AR5K_AR5212) {
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if (ah->ah_version == AR5K_AR5212) {
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/* Restore normal 32/40MHz clock operation
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/* Restore normal 32/40MHz clock operation
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* to avoid register access delay on certain
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* to avoid register access delay on certain
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@@ -1141,8 +1137,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
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ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
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}
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}
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}
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}
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ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
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}
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}
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/* Ledstate */
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/* Ledstate */
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