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drm/i915: use I915_GEM_GPU_DOMAINS

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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Chris Wilson
2009-06-06 09:46:02 +01:00
committed by Eric Anholt
parent b1ce786cb8
commit 21d509e339
1 changed files with 9 additions and 13 deletions
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22
drivers/gpu/drm/i915/i915_gem.c
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@@ -989,10 +989,10 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
return -ENODEV; return -ENODEV;
/* Only handle setting domains to types used by the CPU. */ /* Only handle setting domains to types used by the CPU. */
if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) if (write_domain & I915_GEM_GPU_DOMAINS)
return -EINVAL; return -EINVAL;
if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) if (read_domains & I915_GEM_GPU_DOMAINS)
return -EINVAL; return -EINVAL;
/* Having something in the write domain implies it's in the read /* Having something in the write domain implies it's in the read
@@ -1769,8 +1769,7 @@ i915_gem_flush(struct drm_device *dev,
if (flush_domains & I915_GEM_DOMAIN_CPU) if (flush_domains & I915_GEM_DOMAIN_CPU)
drm_agp_chipset_flush(dev); drm_agp_chipset_flush(dev);
if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
I915_GEM_DOMAIN_GTT)) {
/* /*
* read/write caches: * read/write caches:
* *
@@ -2424,8 +2423,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
* wasn't in the GTT, there shouldn't be any way it could have been in * wasn't in the GTT, there shouldn't be any way it could have been in
* a GPU cache * a GPU cache
*/ */
BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
return 0; return 0;
} }
@@ -3568,8 +3567,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
atomic_inc(&dev->pin_count); atomic_inc(&dev->pin_count);
atomic_add(obj->size, &dev->pin_memory); atomic_add(obj->size, &dev->pin_memory);
if (!obj_priv->active && if (!obj_priv->active &&
(obj->write_domain & ~(I915_GEM_DOMAIN_CPU | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
I915_GEM_DOMAIN_GTT)) == 0 &&
!list_empty(&obj_priv->list)) !list_empty(&obj_priv->list))
list_del_init(&obj_priv->list); list_del_init(&obj_priv->list);
} }
@@ -3596,8 +3594,7 @@ i915_gem_object_unpin(struct drm_gem_object *obj)
*/ */
if (obj_priv->pin_count == 0) { if (obj_priv->pin_count == 0) {
if (!obj_priv->active && if (!obj_priv->active &&
(obj->write_domain & ~(I915_GEM_DOMAIN_CPU | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
I915_GEM_DOMAIN_GTT)) == 0)
list_move_tail(&obj_priv->list, list_move_tail(&obj_priv->list,
&dev_priv->mm.inactive_list); &dev_priv->mm.inactive_list);
atomic_dec(&dev->pin_count); atomic_dec(&dev->pin_count);
@@ -3847,9 +3844,8 @@ i915_gem_idle(struct drm_device *dev)
/* Flush the GPU along with all non-CPU write domains /* Flush the GPU along with all non-CPU write domains
*/ */
i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT), i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
seqno = i915_add_request(dev, NULL, ~I915_GEM_DOMAIN_CPU);
if (seqno == 0) { if (seqno == 0) {
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);