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ARM: OMAP: Split omap_cfg_reg() into omap processor specific functions

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Use omap processor specific function depending on system type.
Based on an earlier patch by Klaus Pedersen <klaus.k.pedersen@nokia.com>.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
2008-01-25 00:42:48 -08:00
parent 7d7f665d5d
commit 225dfda1d6
3 changed files with 139 additions and 137 deletions
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103
arch/arm/mach-omap1/mux.c
View File

@@ -314,7 +314,110 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
{ {
static DEFINE_SPINLOCK(mux_spin_lock);
unsigned long flags;
unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
pull_orig = 0, pull = 0;
unsigned int mask, warn = 0;
/* Check the mux register in question */
if (cfg->mux_reg) {
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
reg_orig = omap_readl(cfg->mux_reg);
/* The mux registers always seem to be 3 bits long */
mask = (0x7 << cfg->mask_offset);
tmp1 = reg_orig & mask;
reg = reg_orig & ~mask;
tmp2 = (cfg->mask << cfg->mask_offset);
reg |= tmp2;
if (tmp1 != tmp2)
warn = 1;
omap_writel(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
/* Check for pull up or pull down selection on 1610 */
if (!cpu_is_omap15xx()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
spin_lock_irqsave(&mux_spin_lock, flags);
pu_pd_orig = omap_readl(cfg->pu_pd_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pu_pd_val) {
if (!(pu_pd_orig & mask))
warn = 1;
/* Use pull up */
pu_pd = pu_pd_orig | mask;
} else {
if (pu_pd_orig & mask)
warn = 1;
/* Use pull down */
pu_pd = pu_pd_orig & ~mask;
}
omap_writel(pu_pd, cfg->pu_pd_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
}
/* Check for an associated pull down register */
if (cfg->pull_reg) {
spin_lock_irqsave(&mux_spin_lock, flags);
pull_orig = omap_readl(cfg->pull_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pull_val) {
if (pull_orig & mask)
warn = 1;
/* Low bit = pull enabled */
pull = pull_orig & ~mask;
} else {
if (!(pull_orig & mask))
warn = 1;
/* High bit = pull disabled */
pull = pull_orig | mask;
}
omap_writel(pull, cfg->pull_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
if (warn) {
#ifdef CONFIG_OMAP_MUX_WARNINGS
printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
}
#ifdef CONFIG_OMAP_MUX_DEBUG
if (cfg->debug || warn) {
printk("MUX: Setting register %s\n", cfg->name);
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
if (!cpu_is_omap15xx()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pu_pd_name, cfg->pu_pd_reg,
pu_pd_orig, pu_pd);
}
}
if (cfg->pull_reg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
#endif
#ifdef CONFIG_OMAP_MUX_ERRORS
return warn ? -ETXTBSY : 0;
#else
return 0; return 0;
#endif
} }
int __init omap1_mux_init(void) int __init omap1_mux_init(void)

31
arch/arm/mach-omap2/mux.c
View File

@@ -172,8 +172,39 @@ MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
}; };
#ifdef CONFIG_ARCH_OMAP24XX #ifdef CONFIG_ARCH_OMAP24XX
#define OMAP24XX_L4_BASE 0x48000000
#define OMAP24XX_PULL_ENA (1 << 3)
#define OMAP24XX_PULL_UP (1 << 4)
/* REVISIT: Convert this code to use ctrl_{read,write}_reg */
int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
{ {
u8 reg = 0;
unsigned int warn = 0;
reg |= cfg->mask & 0x7;
if (cfg->pull_val)
reg |= OMAP24XX_PULL_ENA;
if(cfg->pu_pd_val)
reg |= OMAP24XX_PULL_UP;
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
{
u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
u8 debug = 0;
#ifdef CONFIG_OMAP_MUX_DEBUG
debug = cfg->debug;
#endif
warn = (orig != reg);
if (debug || warn)
printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
orig, reg);
}
#endif
omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
return 0; return 0;
} }
#endif #endif

142
arch/arm/plat-omap/mux.c
View File

@@ -32,10 +32,6 @@
#ifdef CONFIG_OMAP_MUX #ifdef CONFIG_OMAP_MUX
#define OMAP24XX_L4_BASE 0x48000000
#define OMAP24XX_PULL_ENA (1 << 3)
#define OMAP24XX_PULL_UP (1 << 4)
static struct omap_mux_cfg *mux_cfg; static struct omap_mux_cfg *mux_cfg;
int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
@@ -56,13 +52,7 @@ int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
*/ */
int __init_or_module omap_cfg_reg(const unsigned long index) int __init_or_module omap_cfg_reg(const unsigned long index)
{ {
static DEFINE_SPINLOCK(mux_spin_lock); struct pin_config *reg;
unsigned long flags;
struct pin_config *cfg;
unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
pull_orig = 0, pull = 0;
unsigned int mask, warn = 0;
if (mux_cfg == NULL) { if (mux_cfg == NULL) {
printk(KERN_ERR "Pin mux table not initialized\n"); printk(KERN_ERR "Pin mux table not initialized\n");
@@ -76,134 +66,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
return -ENODEV; return -ENODEV;
} }
cfg = (struct pin_config *)&mux_cfg->pins[index]; reg = (struct pin_config *)&mux_cfg->pins[index];
if (cpu_is_omap24xx()) {
u8 reg = 0;
reg |= cfg->mask & 0x7; if (!mux_cfg->cfg_reg)
if (cfg->pull_val) return -ENODEV;
reg |= OMAP24XX_PULL_ENA;
if(cfg->pu_pd_val)
reg |= OMAP24XX_PULL_UP;
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
{
u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
u8 debug = 0;
#ifdef CONFIG_OMAP_MUX_DEBUG return mux_cfg->cfg_reg(reg);
debug = cfg->debug;
#endif
warn = (orig != reg);
if (debug || warn)
printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
cfg->name,
OMAP24XX_L4_BASE + cfg->mux_reg,
orig, reg);
}
#endif
omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
return 0;
}
/* Check the mux register in question */
if (cfg->mux_reg) {
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
reg_orig = omap_readl(cfg->mux_reg);
/* The mux registers always seem to be 3 bits long */
mask = (0x7 << cfg->mask_offset);
tmp1 = reg_orig & mask;
reg = reg_orig & ~mask;
tmp2 = (cfg->mask << cfg->mask_offset);
reg |= tmp2;
if (tmp1 != tmp2)
warn = 1;
omap_writel(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
/* Check for pull up or pull down selection on 1610 */
if (!cpu_is_omap15xx()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
spin_lock_irqsave(&mux_spin_lock, flags);
pu_pd_orig = omap_readl(cfg->pu_pd_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pu_pd_val) {
if (!(pu_pd_orig & mask))
warn = 1;
/* Use pull up */
pu_pd = pu_pd_orig | mask;
} else {
if (pu_pd_orig & mask)
warn = 1;
/* Use pull down */
pu_pd = pu_pd_orig & ~mask;
}
omap_writel(pu_pd, cfg->pu_pd_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
}
/* Check for an associated pull down register */
if (cfg->pull_reg) {
spin_lock_irqsave(&mux_spin_lock, flags);
pull_orig = omap_readl(cfg->pull_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pull_val) {
if (pull_orig & mask)
warn = 1;
/* Low bit = pull enabled */
pull = pull_orig & ~mask;
} else {
if (!(pull_orig & mask))
warn = 1;
/* High bit = pull disabled */
pull = pull_orig | mask;
}
omap_writel(pull, cfg->pull_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
if (warn) {
#ifdef CONFIG_OMAP_MUX_WARNINGS
printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
}
#ifdef CONFIG_OMAP_MUX_DEBUG
if (cfg->debug || warn) {
printk("MUX: Setting register %s\n", cfg->name);
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
if (!cpu_is_omap15xx()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pu_pd_name, cfg->pu_pd_reg,
pu_pd_orig, pu_pd);
}
}
if (cfg->pull_reg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
#endif
#ifdef CONFIG_OMAP_MUX_ERRORS
return warn ? -ETXTBSY : 0;
#else
return 0;
#endif
} }
EXPORT_SYMBOL(omap_cfg_reg); EXPORT_SYMBOL(omap_cfg_reg);
#else #else