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m32r: Convert opsput pld irq chip

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Convert the irq chips to the new functions and use proper flow
handlers. handle_level_irq is appropriate.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Thomas Gleixner
2011-01-19 18:55:09 +01:00
parent 883c0ccde1
commit 22cbc9384a
1 changed files with 20 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
arch/m32r/platforms/opsput/setup.c
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@@ -107,31 +107,23 @@ static void enable_opsput_pld_irq(unsigned int irq)
outw(data, port); outw(data, port);
} }
static void mask_and_ack_opsput_pld(unsigned int irq) static void mask_opsput_pld(struct irq_data *data)
{ {
disable_opsput_pld_irq(irq); disable_opsput_pld_irq(data->irq);
// mask_and_ack_opsput(M32R_IRQ_INT1);
} }
static void end_opsput_pld_irq(unsigned int irq) static void unmask_opsput_pld(struct irq_data *data)
{ {
enable_opsput_pld_irq(irq); enable_opsput_pld_irq(data->irq);
enable_opsput_irq(M32R_IRQ_INT1); enable_opsput_irq(M32R_IRQ_INT1);
} }
static unsigned int startup_opsput_pld_irq(unsigned int irq) static void shutdown_opsput_pld(struct irq_data *data)
{
enable_opsput_pld_irq(irq);
return (0);
}
static void shutdown_opsput_pld_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
unsigned int pldirq; unsigned int pldirq;
pldirq = irq2pldirq(irq); pldirq = irq2pldirq(data->irq);
// shutdown_opsput_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq); port = pldirq2port(pldirq);
outw(PLD_ICUCR_ILEVEL7, port); outw(PLD_ICUCR_ILEVEL7, port);
} }
@@ -139,12 +131,9 @@ static void shutdown_opsput_pld_irq(unsigned int irq)
static struct irq_chip opsput_pld_irq_type = static struct irq_chip opsput_pld_irq_type =
{ {
.name = "OPSPUT-PLD-IRQ", .name = "OPSPUT-PLD-IRQ",
.startup = startup_opsput_pld_irq, .irq_shutdown = shutdown_opsput_pld,
.shutdown = shutdown_opsput_pld_irq, .irq_mask = mask_opsput_pld,
.enable = enable_opsput_pld_irq, .irq_unmask = unmask_opsput_pld,
.disable = disable_opsput_pld_irq,
.ack = mask_and_ack_opsput_pld,
.end = end_opsput_pld_irq
}; };
/* /*
@@ -332,28 +321,33 @@ void __init init_IRQ(void)
#ifdef CONFIG_SERIAL_M32R_PLDSIO #ifdef CONFIG_SERIAL_M32R_PLDSIO
/* INT#1: SIO0 Receive on PLD */ /* INT#1: SIO0 Receive on PLD */
set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
/* INT#1: SIO0 Send on PLD */ /* INT#1: SIO0 Send on PLD */
set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
#endif /* CONFIG_SERIAL_M32R_PLDSIO */ #endif /* CONFIG_SERIAL_M32R_PLDSIO */
/* INT#1: CFC IREQ on PLD */ /* INT#1: CFC IREQ on PLD */
set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
disable_opsput_pld_irq(PLD_IRQ_CFIREQ); disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
/* INT#1: CFC Insert on PLD */ /* INT#1: CFC Insert on PLD */
set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
/* INT#1: CFC Eject on PLD */ /* INT#1: CFC Eject on PLD */
set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);