[MIPS] RM: Collected changes
- EISA support for non PCI RMs (RM200 and RM400-xxx). The major part is the splitting of the EISA and onboard ISA of the RM200, which makes the EISA bus on the RM200 look like on other RMs. - 64bit kernel support - system type detection is now common for big and little endian - moved sniprom code to arch/mips/fw - added call_o32 function to arch/mips/fw/lib, which uses a private stack for calling prom functions - fix problem with ISA interrupts, which makes using PIT clockevent possible Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer
committed by
Ralf Baechle
Ralf Baechle
parent
237cfee1db
commit
231a35d372
@@ -5,30 +5,36 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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* Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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*
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* i8259 parts ripped out of arch/mips/kernel/i8259.c
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/io.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#include <asm/irq_cpu.h>
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#define PORT(_base,_irq) \
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#define RM200_I8259A_IRQ_BASE 32
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#define MEMPORT(_base,_irq) \
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{ \
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.iobase = _base, \
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.mapbase = _base, \
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.irq = _irq, \
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.uartclk = 1843200, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF, \
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.iotype = UPIO_MEM, \
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.flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \
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}
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static struct plat_serial8250_port rm200_data[] = {
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PORT(0x3f8, 4),
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PORT(0x2f8, 3),
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MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
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MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
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{ },
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};
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@@ -112,15 +118,311 @@ static int __init snirm_setup_devinit(void)
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platform_device_register(&rm200_ds1216_device);
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platform_device_register(&snirm_82596_rm200_pdev);
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platform_device_register(&snirm_53c710_rm200_pdev);
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sni_eisa_root_init();
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}
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return 0;
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}
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device_initcall(snirm_setup_devinit);
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/*
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* RM200 has an ISA and an EISA bus. The iSA bus is only used
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* for onboard devices and also has twi i8259 PICs. Since these
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* PICs are no accessible via inb/outb the following code uses
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* readb/writeb to access them
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*/
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#define SNI_RM200_INT_STAT_REG 0xbc000000
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#define SNI_RM200_INT_ENA_REG 0xbc080000
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DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
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#define PIC_CMD 0x00
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#define PIC_IMR 0x01
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#define PIC_ISR PIC_CMD
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#define PIC_POLL PIC_ISR
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#define PIC_OCW3 PIC_ISR
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/* i8259A PIC related value */
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#define PIC_CASCADE_IR 2
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#define MASTER_ICW4_DEFAULT 0x01
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#define SLAVE_ICW4_DEFAULT 0x01
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/*
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* This contains the irq mask for both 8259A irq controllers,
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*/
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static unsigned int rm200_cached_irq_mask = 0xffff;
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static __iomem u8 *rm200_pic_master;
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static __iomem u8 *rm200_pic_slave;
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#define cached_master_mask (rm200_cached_irq_mask)
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#define cached_slave_mask (rm200_cached_irq_mask >> 8)
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static void sni_rm200_disable_8259A_irq(unsigned int irq)
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{
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unsigned int mask;
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unsigned long flags;
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irq -= RM200_I8259A_IRQ_BASE;
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mask = 1 << irq;
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spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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rm200_cached_irq_mask |= mask;
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if (irq & 8)
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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else
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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}
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static void sni_rm200_enable_8259A_irq(unsigned int irq)
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{
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unsigned int mask;
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unsigned long flags;
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irq -= RM200_I8259A_IRQ_BASE;
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mask = ~(1 << irq);
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spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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rm200_cached_irq_mask &= mask;
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if (irq & 8)
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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else
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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}
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static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
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{
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int value;
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int irqmask = 1 << irq;
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if (irq < 8) {
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writeb(0x0B, rm200_pic_master + PIC_CMD);
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value = readb(rm200_pic_master + PIC_CMD) & irqmask;
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writeb(0x0A, rm200_pic_master + PIC_CMD);
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return value;
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}
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writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */
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value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8);
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writeb(0x0A, rm200_pic_slave + PIC_CMD);
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return value;
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}
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/*
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* Careful! The 8259A is a fragile beast, it pretty
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* much _has_ to be done exactly like this (mask it
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* first, _then_ send the EOI, and the order of EOI
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* to the two 8259s is important!
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*/
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void sni_rm200_mask_and_ack_8259A(unsigned int irq)
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{
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unsigned int irqmask;
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unsigned long flags;
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irq -= RM200_I8259A_IRQ_BASE;
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irqmask = 1 << irq;
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spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want
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* to overdo spurious IRQ handling - it's usually a sign
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* of hardware problems, so we only do the checks we can
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* do without slowing down good hardware unnecessarily.
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*
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* Note that IRQ7 and IRQ15 (the two spurious IRQs
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* usually resulting from the 8259A-1|2 PICs) occur
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* even if the IRQ is masked in the 8259A. Thus we
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* can check spurious 8259A IRQs without doing the
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* quite slow i8259A_irq_real() call for every IRQ.
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* This does not cover 100% of spurious interrupts,
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* but should be enough to warn the user that there
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* is something bad going on ...
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*/
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if (rm200_cached_irq_mask & irqmask)
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goto spurious_8259A_irq;
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rm200_cached_irq_mask |= irqmask;
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handle_real_irq:
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if (irq & 8) {
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readb(rm200_pic_slave + PIC_IMR);
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);
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writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);
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} else {
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readb(rm200_pic_master + PIC_IMR);
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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writeb(0x60+irq, rm200_pic_master + PIC_CMD);
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}
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spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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/*
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* this is the slow path - should happen rarely.
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*/
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if (sni_rm200_i8259A_irq_real(irq))
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/*
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* oops, the IRQ _is_ in service according to the
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* 8259A - not spurious, go handle it.
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*/
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goto handle_real_irq;
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{
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static int spurious_irq_mask;
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/*
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* At this point we can be sure the IRQ is spurious,
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* lets ACK and report it. [once per IRQ]
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*/
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if (!(spurious_irq_mask & irqmask)) {
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printk(KERN_DEBUG
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"spurious RM200 8259A interrupt: IRQ%d.\n", irq);
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spurious_irq_mask |= irqmask;
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}
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atomic_inc(&irq_err_count);
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/*
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* Theoretically we do not have to handle this IRQ,
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* but in Linux this does not cause problems and is
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* simpler for us.
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*/
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goto handle_real_irq;
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}
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}
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static struct irq_chip sni_rm200_i8259A_chip = {
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.name = "RM200-XT-PIC",
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.mask = sni_rm200_disable_8259A_irq,
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.unmask = sni_rm200_enable_8259A_irq,
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.mask_ack = sni_rm200_mask_and_ack_8259A,
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};
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/*
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* Do the traditional i8259 interrupt polling thing. This is for the few
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* cases where no better interrupt acknowledge method is available and we
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* absolutely must touch the i8259.
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*/
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static inline int sni_rm200_i8259_irq(void)
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{
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int irq;
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spin_lock(&sni_rm200_i8259A_lock);
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/* Perform an interrupt acknowledge cycle on controller 1. */
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writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
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irq = readb(rm200_pic_master + PIC_CMD) & 7;
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if (irq == PIC_CASCADE_IR) {
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/*
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* Interrupt is cascaded so perform interrupt
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* acknowledge on controller 2.
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*/
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writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */
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irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8;
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}
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if (unlikely(irq == 7)) {
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/*
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* This may be a spurious interrupt.
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*
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* Read the interrupt status register (ISR). If the most
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* significant bit is not set then there is no valid
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* interrupt.
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*/
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writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */
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if (~readb(rm200_pic_master + PIC_ISR) & 0x80)
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irq = -1;
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}
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spin_unlock(&sni_rm200_i8259A_lock);
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return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;
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}
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void sni_rm200_init_8259A(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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writeb(0xff, rm200_pic_master + PIC_IMR);
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writeb(0xff, rm200_pic_slave + PIC_IMR);
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writeb(0x11, rm200_pic_master + PIC_CMD);
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writeb(0, rm200_pic_master + PIC_IMR);
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writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);
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writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);
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writeb(0x11, rm200_pic_slave + PIC_CMD);
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writeb(8, rm200_pic_slave + PIC_IMR);
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writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);
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writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);
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udelay(100); /* wait for 8259A to initialize */
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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}
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction sni_rm200_irq2 = {
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no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
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};
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static struct resource sni_rm200_pic1_resource = {
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.name = "onboard ISA pic1",
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.start = 0x16000020,
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.end = 0x16000023,
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.flags = IORESOURCE_BUSY
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};
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static struct resource sni_rm200_pic2_resource = {
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.name = "onboard ISA pic2",
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.start = 0x160000a0,
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.end = 0x160000a3,
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.flags = IORESOURCE_BUSY
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};
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/* ISA irq handler */
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static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p)
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{
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int irq;
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irq = sni_rm200_i8259_irq();
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if (unlikely(irq < 0))
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return IRQ_NONE;
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do_IRQ(irq);
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return IRQ_HANDLED;
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}
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struct irqaction sni_rm200_i8259A_irq = {
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.handler = sni_rm200_i8259A_irq_handler,
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.name = "onboard ISA",
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.flags = IRQF_SHARED
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};
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void __init sni_rm200_i8259_irqs(void)
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{
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int i;
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rm200_pic_master = ioremap_nocache(0x16000020, 4);
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if (!rm200_pic_master)
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return;
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rm200_pic_slave = ioremap_nocache(0x160000a0, 4);
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if (!rm200_pic_master) {
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iounmap(rm200_pic_master);
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return;
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}
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insert_resource(&iomem_resource, &sni_rm200_pic1_resource);
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insert_resource(&iomem_resource, &sni_rm200_pic2_resource);
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sni_rm200_init_8259A();
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for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
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set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip,
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handle_level_irq);
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setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
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}
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#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)
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#define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000)
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#define SNI_RM200_INT_START 24
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#define SNI_RM200_INT_END 28
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@@ -181,17 +483,17 @@ void __init sni_rm200_irq_init(void)
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* (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f;
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sni_rm200_i8259_irqs();
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mips_cpu_irq_init();
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/* Actually we've got more interrupts to handle ... */
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for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
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set_irq_chip(i, &rm200_irq_type);
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sni_hwint = sni_rm200_hwint;
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change_c0_status(ST0_IM, IE_IRQ0);
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setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq);
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setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
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setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq);
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}
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void __init sni_rm200_init(void)
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{
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set_io_port_base(SNI_PORT_BASE + 0x02000000);
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ioport_resource.end += 0x02000000;
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}
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