[MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines
This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines. GT64111 PCI is almost the same as GT64120's PCI_0. This patch don't change GT64120 PCI routines. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
committed by
Ralf Baechle
Ralf Baechle
parent
2a9effc678
commit
252161eccd
@ -8,8 +8,7 @@ obj-y += pci.o pci-dac.o
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# PCI bus host bridge specific code
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#
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obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
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obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o
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obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
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obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
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obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
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obj-$(CONFIG_MIPS_MSC) += ops-msc.o
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obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
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@ -1,100 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <asm/gt64120.h>
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#include <asm/mach-cobalt/cobalt.h>
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/*
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* Device 31 on the GT64111 is used to generate PCI special
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* cycles, so we shouldn't expected to find a device there ...
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*/
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static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
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{
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if (bus->number == 0 && PCI_SLOT(devfn) < 31)
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return 0;
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return -1;
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}
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static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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if (pci_range_ck(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 4:
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PCI_CFG_SET(devfn, where);
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*val = GT_READ(GT_PCI0_CFGDATA_OFS);
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return PCIBIOS_SUCCESSFUL;
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case 2:
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PCI_CFG_SET(devfn, (where & ~0x3));
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*val = GT_READ(GT_PCI0_CFGDATA_OFS)
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>> ((where & 3) * 8);
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return PCIBIOS_SUCCESSFUL;
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case 1:
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PCI_CFG_SET(devfn, (where & ~0x3));
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*val = GT_READ(GT_PCI0_CFGDATA_OFS)
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>> ((where & 3) * 8);
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return PCIBIOS_SUCCESSFUL;
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}
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 tmp;
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if (pci_range_ck(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 4:
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PCI_CFG_SET(devfn, where);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
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return PCIBIOS_SUCCESSFUL;
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case 2:
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PCI_CFG_SET(devfn, (where & ~0x3));
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tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
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tmp &= ~(0xffff << ((where & 0x3) * 8));
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tmp |= (val << ((where & 0x3) * 8));
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GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
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return PCIBIOS_SUCCESSFUL;
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case 1:
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PCI_CFG_SET(devfn, (where & ~0x3));
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tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
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tmp &= ~(0xff << ((where & 0x3) * 8));
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tmp |= (val << ((where & 0x3) * 8));
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GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
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return PCIBIOS_SUCCESSFUL;
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}
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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struct pci_ops gt64111_pci_ops = {
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.read = gt64111_pci_read_config,
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.write = gt64111_pci_write_config,
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};
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@ -39,8 +39,8 @@
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#define PCI_CFG_TYPE1_DEV_SHF 11
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#define PCI_CFG_TYPE1_BUS_SHF 16
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static int gt64120_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
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static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
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{
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unsigned char busnum = bus->number;
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u32 intr;
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@ -100,13 +100,13 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
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&data))
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
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where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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@ -119,16 +119,16 @@ static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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return PCIBIOS_SUCCESSFUL;
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}
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static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4)
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data = val;
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else {
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if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
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where, &data))
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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@ -139,14 +139,14 @@ static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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(val << ((where & 3) << 3));
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}
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if (gt64120_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
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&data))
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
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where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops gt64120_pci_ops = {
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.read = gt64120_pcibios_read,
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.write = gt64120_pcibios_write
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struct pci_ops gt64xxx_pci0_ops = {
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.read = gt64xxx_pci0_pcibios_read,
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.write = gt64xxx_pci0_pcibios_write
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};
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@ -12,7 +12,7 @@
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#include <asm/bootinfo.h>
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extern struct pci_ops nile4_pci_ops;
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extern struct pci_ops gt64120_pci_ops;
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extern struct pci_ops gt64xxx_pci0_ops;
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static struct resource lasat_pci_mem_resource = {
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.name = "LASAT PCI MEM",
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.start = 0x18000000,
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@ -38,7 +38,7 @@ static int __init lasat_pci_setup(void)
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switch (mips_machtype) {
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case MACH_LASAT_100:
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lasat_pci_controller.pci_ops = >64120_pci_ops;
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lasat_pci_controller.pci_ops = >64xxx_pci0_ops;
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break;
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case MACH_LASAT_200:
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lasat_pci_controller.pci_ops = &nile4_pci_ops;
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@ -81,7 +81,7 @@ static struct resource ocelot_io_resource = {
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};
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static struct pci_controller ocelot_pci_controller = {
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.pci_ops = gt64120_pci_ops;
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.pci_ops = gt64xxx_pci0_ops;
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.mem_resource = &ocelot_mem_resource;
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.io_resource = &ocelot_io_resource;
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};
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