ide: remove ide_setup_ports()
ide-cris.c: * Add cris_setup_ports() helper and use it instead of ide_setup_ports() (fixes random value being set in ->io_ports[IDE_IRQ_OFFSET]). buddha.c: * Add buddha_setup_ports() helper and use it instead of ide_setup_ports(). falconide.c: * Add falconide_setup_ports() helper and use it instead of ide_setup_ports(), also fix return value of falconide_init() while at it. gayle.c: * Add gayle_setup_ports() helper and use it instead of ide_setup_ports(). macide.c: * Add macide_setup_ports() helper and use it instead of ide_setup_ports() (fixes incorrect value being set in ->io_ports[IDE_IRQ_OFFSET]). q40ide.c: * Fix q40_ide_setup_ports() comments. ide.c: * Remove no longer needed ide_setup_ports(). Cc: Mikael Starvik <starvik@axis.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
@@ -753,6 +753,25 @@ static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
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cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
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cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
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}
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}
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static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
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{
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int i;
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memset(hw, 0, sizeof(*hw));
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for (i = 0; i <= 7; i++)
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hw->io_ports[i] = base + cris_ide_reg_addr(i, 0, 1);
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/*
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* the IDE control register is at ATA address 6,
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* with CS1 active instead of CS0
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*/
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hw->io_ports[IDE_CONTROL_OFFSET] = base + cris_ide_reg_addr(6, 1, 0);
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hw->irq = ide_default_irq(0);
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hw->ack_intr = cris_ide_ack_intr;
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}
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static const struct ide_port_info cris_port_info __initdata = {
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static const struct ide_port_info cris_port_info __initdata = {
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.chipset = ide_etrax100,
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.chipset = ide_etrax100,
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA |
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA |
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@@ -765,24 +784,16 @@ static const struct ide_port_info cris_port_info __initdata = {
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static int __init init_e100_ide(void)
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static int __init init_e100_ide(void)
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{
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{
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hw_regs_t hw;
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hw_regs_t hw;
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int ide_offsets[IDE_NR_PORTS], h, i;
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int h;
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u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
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u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
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printk("ide: ETRAX FS built-in ATA DMA controller\n");
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printk("ide: ETRAX FS built-in ATA DMA controller\n");
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for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
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ide_offsets[i] = cris_ide_reg_addr(i, 0, 1);
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/* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
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ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0);
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for (h = 0; h < 4; h++) {
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for (h = 0; h < 4; h++) {
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ide_hwif_t *hwif = NULL;
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ide_hwif_t *hwif = NULL;
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ide_setup_ports(&hw, cris_ide_base_address(h),
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cris_setup_ports(&hw, cris_ide_base_address(h));
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ide_offsets,
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0, 0, cris_ide_ack_intr,
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ide_default_irq(0));
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hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
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hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
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if (hwif == NULL)
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if (hwif == NULL)
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continue;
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continue;
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@@ -618,60 +618,6 @@ abort:
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EXPORT_SYMBOL(ide_unregister);
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EXPORT_SYMBOL(ide_unregister);
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/**
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* ide_setup_ports - set up IDE interface ports
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* @hw: register descriptions
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* @base: base register
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* @offsets: table of register offsets
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* @ctrl: control register
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* @ack_irq: IRQ ack
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* @irq: interrupt lie
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*
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* Setup hw_regs_t structure described by parameters. You
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* may set up the hw structure yourself OR use this routine to
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* do it for you. This is basically a helper
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*
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*/
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void ide_setup_ports ( hw_regs_t *hw,
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unsigned long base, int *offsets,
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unsigned long ctrl, unsigned long intr,
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ide_ack_intr_t *ack_intr,
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/*
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* ide_io_ops_t *iops,
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*/
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int irq)
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{
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int i;
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memset(hw, 0, sizeof(hw_regs_t));
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for (i = 0; i < IDE_NR_PORTS; i++) {
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if (offsets[i] == -1) {
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switch(i) {
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case IDE_CONTROL_OFFSET:
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hw->io_ports[i] = ctrl;
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break;
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#if defined(CONFIG_AMIGA) || defined(CONFIG_MAC)
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case IDE_IRQ_OFFSET:
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hw->io_ports[i] = intr;
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break;
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#endif /* (CONFIG_AMIGA) || (CONFIG_MAC) */
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default:
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hw->io_ports[i] = 0;
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break;
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}
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} else {
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hw->io_ports[i] = base + offsets[i];
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}
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}
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hw->irq = irq;
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hw->ack_intr = ack_intr;
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/*
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* hw->iops = iops;
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*/
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}
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void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw)
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void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw)
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{
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{
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memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
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memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
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@@ -56,31 +56,11 @@ static u_int xsurf_bases[XSURF_NUM_HWIFS] __initdata = {
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XSURF_BASE1, XSURF_BASE2
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XSURF_BASE1, XSURF_BASE2
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};
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};
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/*
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/*
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* Offsets from one of the above bases
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* Offsets from one of the above bases
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*/
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*/
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#define BUDDHA_DATA 0x00
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#define BUDDHA_ERROR 0x06 /* see err-bits */
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#define BUDDHA_NSECTOR 0x0a /* nr of sectors to read/write */
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#define BUDDHA_SECTOR 0x0e /* starting sector */
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#define BUDDHA_LCYL 0x12 /* starting cylinder */
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#define BUDDHA_HCYL 0x16 /* high byte of starting cyl */
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#define BUDDHA_SELECT 0x1a /* 101dhhhh , d=drive, hhhh=head */
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#define BUDDHA_STATUS 0x1e /* see status-bits */
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#define BUDDHA_CONTROL 0x11a
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#define BUDDHA_CONTROL 0x11a
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#define XSURF_CONTROL -1 /* X-Surf has no CS1* (Control/AltStat) */
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static int buddha_offsets[IDE_NR_PORTS] __initdata = {
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BUDDHA_DATA, BUDDHA_ERROR, BUDDHA_NSECTOR, BUDDHA_SECTOR, BUDDHA_LCYL,
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BUDDHA_HCYL, BUDDHA_SELECT, BUDDHA_STATUS, BUDDHA_CONTROL, -1
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};
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static int xsurf_offsets[IDE_NR_PORTS] __initdata = {
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BUDDHA_DATA, BUDDHA_ERROR, BUDDHA_NSECTOR, BUDDHA_SECTOR, BUDDHA_LCYL,
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BUDDHA_HCYL, BUDDHA_SELECT, BUDDHA_STATUS, XSURF_CONTROL, -1
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};
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/*
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/*
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* Other registers
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* Other registers
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@@ -140,6 +120,26 @@ static int xsurf_ack_intr(ide_hwif_t *hwif)
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return 1;
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return 1;
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}
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}
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static void __init buddha_setup_ports(hw_regs_t *hw, unsigned long base,
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unsigned long ctl, unsigned long irq_port,
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ide_ack_intr_t *ack_intr)
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{
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int i;
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memset(hw, 0, sizeof(*hw));
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hw->io_ports[IDE_DATA_OFFSET] = base;
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for (i = 1; i < 8; i++)
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hw->io_ports[i] = base + 2 + i * 4;
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hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
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hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
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hw->irq = IRQ_AMIGA_PORTS;
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hw->ack_intr = ack_intr;
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}
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/*
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/*
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* Probe for a Buddha or Catweasel IDE interface
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* Probe for a Buddha or Catweasel IDE interface
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*/
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*/
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@@ -202,22 +202,24 @@ fail_base2:
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printk(KERN_INFO "ide: %s IDE controller\n",
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printk(KERN_INFO "ide: %s IDE controller\n",
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buddha_board_name[type]);
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buddha_board_name[type]);
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for(i=0;i<buddha_num_hwifs;i++) {
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for (i = 0; i < buddha_num_hwifs; i++) {
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if(type != BOARD_XSURF) {
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unsigned long base, ctl, irq_port;
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ide_setup_ports(&hw, (buddha_board+buddha_bases[i]),
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ide_ack_intr_t *ack_intr;
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buddha_offsets, 0,
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(buddha_board+buddha_irqports[i]),
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if (type != BOARD_XSURF) {
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buddha_ack_intr,
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base = buddha_board + buddha_bases[i];
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// budda_iops,
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ctl = base + BUDDHA_CONTROL;
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IRQ_AMIGA_PORTS);
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irq_port = buddha_board + buddha_irqports[i];
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ack_intr = buddha_ack_intr;
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} else {
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} else {
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ide_setup_ports(&hw, (buddha_board+xsurf_bases[i]),
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base = buddha_board + xsurf_bases[i];
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xsurf_offsets, 0,
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/* X-Surf has no CS1* (Control/AltStat) */
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(buddha_board+xsurf_irqports[i]),
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ctl = 0;
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xsurf_ack_intr,
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irq_port = buddha_board + xsurf_irqports[i];
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// xsurf_iops,
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ack_intr = xsurf_ack_intr;
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IRQ_AMIGA_PORTS);
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}
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}
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buddha_setup_ports(&hw, base, ctl, irq_port, ack_intr);
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hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
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hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
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if (hwif) {
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if (hwif) {
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@@ -33,22 +33,8 @@
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* Offsets from the above base
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* Offsets from the above base
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*/
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*/
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#define ATA_HD_DATA 0x00
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#define ATA_HD_ERROR 0x05 /* see err-bits */
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#define ATA_HD_NSECTOR 0x09 /* nr of sectors to read/write */
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#define ATA_HD_SECTOR 0x0d /* starting sector */
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#define ATA_HD_LCYL 0x11 /* starting cylinder */
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#define ATA_HD_HCYL 0x15 /* high byte of starting cyl */
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#define ATA_HD_SELECT 0x19 /* 101dhhhh , d=drive, hhhh=head */
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#define ATA_HD_STATUS 0x1d /* see status-bits */
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#define ATA_HD_CONTROL 0x39
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#define ATA_HD_CONTROL 0x39
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static int falconide_offsets[IDE_NR_PORTS] __initdata = {
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ATA_HD_DATA, ATA_HD_ERROR, ATA_HD_NSECTOR, ATA_HD_SECTOR, ATA_HD_LCYL,
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ATA_HD_HCYL, ATA_HD_SELECT, ATA_HD_STATUS, ATA_HD_CONTROL, -1
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};
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/*
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/*
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* falconide_intr_lock is used to obtain access to the IDE interrupt,
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* falconide_intr_lock is used to obtain access to the IDE interrupt,
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* which is shared between several drivers.
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* which is shared between several drivers.
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@@ -57,6 +43,22 @@ static int falconide_offsets[IDE_NR_PORTS] __initdata = {
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int falconide_intr_lock;
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int falconide_intr_lock;
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EXPORT_SYMBOL(falconide_intr_lock);
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EXPORT_SYMBOL(falconide_intr_lock);
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static void __init falconide_setup_ports(hw_regs_t *hw)
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{
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int i;
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memset(hw, 0, sizeof(*hw));
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hw->io_ports[IDE_DATA_OFFSET] = ATA_HD_BASE;
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for (i = 1; i < 8; i++)
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hw->io_ports[i] = ATA_HD_BASE + 1 + i * 4;
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hw->io_ports[IDE_CONTROL_OFFSET] = ATA_HD_CONTROL;
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hw->irq = IRQ_MFP_IDE;
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hw->ack_intr = NULL;
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}
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/*
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/*
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* Probe for a Falcon IDE interface
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* Probe for a Falcon IDE interface
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@@ -64,16 +66,15 @@ EXPORT_SYMBOL(falconide_intr_lock);
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static int __init falconide_init(void)
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static int __init falconide_init(void)
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{
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{
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if (MACH_IS_ATARI && ATARIHW_PRESENT(IDE)) {
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hw_regs_t hw;
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hw_regs_t hw;
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ide_hwif_t *hwif;
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ide_hwif_t *hwif;
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if (!MACH_IS_ATARI || !ATARIHW_PRESENT(IDE))
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return 0;
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printk(KERN_INFO "ide: Falcon IDE controller\n");
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printk(KERN_INFO "ide: Falcon IDE controller\n");
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ide_setup_ports(&hw, ATA_HD_BASE, falconide_offsets,
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falconide_setup_ports(&hw);
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0, 0, NULL,
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// falconide_iops,
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IRQ_MFP_IDE);
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hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
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hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
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if (hwif) {
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if (hwif) {
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@@ -85,9 +86,8 @@ static int __init falconide_init(void)
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ide_device_add(idx, NULL);
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ide_device_add(idx, NULL);
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}
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}
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}
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return 0;
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return 0;
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}
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}
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module_init(falconide_init);
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module_init(falconide_init);
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@@ -34,22 +34,8 @@
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* Offsets from one of the above bases
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* Offsets from one of the above bases
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*/
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*/
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#define GAYLE_DATA 0x00
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#define GAYLE_ERROR 0x06 /* see err-bits */
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#define GAYLE_NSECTOR 0x0a /* nr of sectors to read/write */
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#define GAYLE_SECTOR 0x0e /* starting sector */
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#define GAYLE_LCYL 0x12 /* starting cylinder */
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#define GAYLE_HCYL 0x16 /* high byte of starting cyl */
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#define GAYLE_SELECT 0x1a /* 101dhhhh , d=drive, hhhh=head */
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#define GAYLE_STATUS 0x1e /* see status-bits */
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#define GAYLE_CONTROL 0x101a
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#define GAYLE_CONTROL 0x101a
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static int gayle_offsets[IDE_NR_PORTS] __initdata = {
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GAYLE_DATA, GAYLE_ERROR, GAYLE_NSECTOR, GAYLE_SECTOR, GAYLE_LCYL,
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GAYLE_HCYL, GAYLE_SELECT, GAYLE_STATUS, -1, -1
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};
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/*
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/*
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* These are at different offsets from the base
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* These are at different offsets from the base
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*/
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*/
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@@ -106,6 +92,26 @@ static int gayle_ack_intr_a1200(ide_hwif_t *hwif)
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return 1;
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return 1;
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}
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}
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static void __init gayle_setup_ports(hw_regs_t *hw, unsigned long base,
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unsigned long ctl, unsigned long irq_port,
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ide_ack_intr_t *ack_intr);
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{
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int i;
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memset(hw, 0, sizeof(*hw));
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hw->io_ports[IDE_DATA_OFFSET] = base;
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for (i = 1; i < 8; i++)
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hw->io_ports[i] = base + 2 + i * 4;
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|
||||||
|
hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
|
||||||
|
hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
|
||||||
|
|
||||||
|
hw->irq = IRQ_AMIGA_PORTS;
|
||||||
|
hw->ack_intr = ack_intr;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Probe for a Gayle IDE interface (and optionally for an IDE doubler)
|
* Probe for a Gayle IDE interface (and optionally for an IDE doubler)
|
||||||
*/
|
*/
|
||||||
@@ -167,10 +173,7 @@ found:
|
|||||||
base = (unsigned long)ZTWO_VADDR(phys_base);
|
base = (unsigned long)ZTWO_VADDR(phys_base);
|
||||||
ctrlport = GAYLE_HAS_CONTROL_REG ? (base + GAYLE_CONTROL) : 0;
|
ctrlport = GAYLE_HAS_CONTROL_REG ? (base + GAYLE_CONTROL) : 0;
|
||||||
|
|
||||||
ide_setup_ports(&hw, base, gayle_offsets,
|
gayle_setup_ports(&hw, base, ctrlport, irqport, ack_intr);
|
||||||
ctrlport, irqport, ack_intr,
|
|
||||||
// &gayle_iops,
|
|
||||||
IRQ_AMIGA_PORTS);
|
|
||||||
|
|
||||||
hwif = ide_find_port(base);
|
hwif = ide_find_port(base);
|
||||||
if (hwif) {
|
if (hwif) {
|
||||||
|
@@ -31,14 +31,6 @@
|
|||||||
* These match MkLinux so they should be correct.
|
* These match MkLinux so they should be correct.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define IDE_DATA 0x00
|
|
||||||
#define IDE_ERROR 0x04 /* see err-bits */
|
|
||||||
#define IDE_NSECTOR 0x08 /* nr of sectors to read/write */
|
|
||||||
#define IDE_SECTOR 0x0c /* starting sector */
|
|
||||||
#define IDE_LCYL 0x10 /* starting cylinder */
|
|
||||||
#define IDE_HCYL 0x14 /* high byte of starting cyl */
|
|
||||||
#define IDE_SELECT 0x18 /* 101dhhhh , d=drive, hhhh=head */
|
|
||||||
#define IDE_STATUS 0x1c /* see status-bits */
|
|
||||||
#define IDE_CONTROL 0x38 /* control/altstatus */
|
#define IDE_CONTROL 0x38 /* control/altstatus */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@@ -63,11 +55,6 @@
|
|||||||
|
|
||||||
volatile unsigned char *ide_ifr = (unsigned char *) (IDE_BASE + IDE_IFR);
|
volatile unsigned char *ide_ifr = (unsigned char *) (IDE_BASE + IDE_IFR);
|
||||||
|
|
||||||
static int macide_offsets[IDE_NR_PORTS] = {
|
|
||||||
IDE_DATA, IDE_ERROR, IDE_NSECTOR, IDE_SECTOR, IDE_LCYL,
|
|
||||||
IDE_HCYL, IDE_SELECT, IDE_STATUS, IDE_CONTROL
|
|
||||||
};
|
|
||||||
|
|
||||||
int macide_ack_intr(ide_hwif_t* hwif)
|
int macide_ack_intr(ide_hwif_t* hwif)
|
||||||
{
|
{
|
||||||
if (*ide_ifr & 0x20) {
|
if (*ide_ifr & 0x20) {
|
||||||
@@ -77,6 +64,22 @@ int macide_ack_intr(ide_hwif_t* hwif)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void __init macide_setup_ports(hw_regs_t *hw, unsigned long base,
|
||||||
|
int irq, ide_ack_intr_t *ack_intr)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
memset(hw, 0, sizeof(*hw));
|
||||||
|
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
hw->io_ports[i] = base + i * 4;
|
||||||
|
|
||||||
|
hw->io_ports[IDE_CONTROL_OFFSET] = IDE_CONTROL;
|
||||||
|
|
||||||
|
hw->irq = irq;
|
||||||
|
hw->ack_intr = ack_intr;
|
||||||
|
}
|
||||||
|
|
||||||
static const char *mac_ide_name[] =
|
static const char *mac_ide_name[] =
|
||||||
{ "Quadra", "Powerbook", "Powerbook Baboon" };
|
{ "Quadra", "Powerbook", "Powerbook Baboon" };
|
||||||
|
|
||||||
@@ -86,27 +89,27 @@ static const char *mac_ide_name[] =
|
|||||||
|
|
||||||
static int __init macide_init(void)
|
static int __init macide_init(void)
|
||||||
{
|
{
|
||||||
hw_regs_t hw;
|
|
||||||
ide_hwif_t *hwif;
|
ide_hwif_t *hwif;
|
||||||
|
ide_ack_intr_t *ack_intr;
|
||||||
|
unsigned long base;
|
||||||
|
int irq;
|
||||||
|
hw_regs_t hw;
|
||||||
|
|
||||||
switch (macintosh_config->ide_type) {
|
switch (macintosh_config->ide_type) {
|
||||||
case MAC_IDE_QUADRA:
|
case MAC_IDE_QUADRA:
|
||||||
ide_setup_ports(&hw, IDE_BASE, macide_offsets,
|
base = IDE_BASE;
|
||||||
0, 0, macide_ack_intr,
|
ack_intr = macide_ack_intr;
|
||||||
// quadra_ide_iops,
|
irq = IRQ_NUBUS_F;
|
||||||
IRQ_NUBUS_F);
|
|
||||||
break;
|
break;
|
||||||
case MAC_IDE_PB:
|
case MAC_IDE_PB:
|
||||||
ide_setup_ports(&hw, IDE_BASE, macide_offsets,
|
base = IDE_BASE;
|
||||||
0, 0, macide_ack_intr,
|
ack_intr = macide_ack_intr;
|
||||||
// macide_pb_iops,
|
irq = IRQ_NUBUS_C;
|
||||||
IRQ_NUBUS_C);
|
|
||||||
break;
|
break;
|
||||||
case MAC_IDE_BABOON:
|
case MAC_IDE_BABOON:
|
||||||
ide_setup_ports(&hw, BABOON_BASE, macide_offsets,
|
base = BABOON_BASE;
|
||||||
0, 0, NULL,
|
ack_intr = NULL;
|
||||||
// macide_baboon_iops,
|
irq = IRQ_BABOON_1;
|
||||||
IRQ_BABOON_1);
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
@@ -115,6 +118,8 @@ static int __init macide_init(void)
|
|||||||
printk(KERN_INFO "ide: Macintosh %s IDE controller\n",
|
printk(KERN_INFO "ide: Macintosh %s IDE controller\n",
|
||||||
mac_ide_name[macintosh_config->ide_type - 1]);
|
mac_ide_name[macintosh_config->ide_type - 1]);
|
||||||
|
|
||||||
|
macide_setup_ports(&hw, base, irq, ack_intr);
|
||||||
|
|
||||||
hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
|
hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
|
||||||
if (hwif) {
|
if (hwif) {
|
||||||
u8 index = hwif->index;
|
u8 index = hwif->index;
|
||||||
|
@@ -66,16 +66,12 @@ static int q40ide_default_irq(unsigned long base)
|
|||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This is very similar to ide_setup_ports except that addresses
|
* Addresses are pretranslated for Q40 ISA access.
|
||||||
* are pretranslated for q40 ISA access
|
|
||||||
*/
|
*/
|
||||||
void q40_ide_setup_ports ( hw_regs_t *hw,
|
void q40_ide_setup_ports ( hw_regs_t *hw,
|
||||||
unsigned long base, int *offsets,
|
unsigned long base, int *offsets,
|
||||||
unsigned long ctrl, unsigned long intr,
|
unsigned long ctrl, unsigned long intr,
|
||||||
ide_ack_intr_t *ack_intr,
|
ide_ack_intr_t *ack_intr,
|
||||||
/*
|
|
||||||
* ide_io_ops_t *iops,
|
|
||||||
*/
|
|
||||||
int irq)
|
int irq)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
@@ -92,9 +88,6 @@ void q40_ide_setup_ports ( hw_regs_t *hw,
|
|||||||
|
|
||||||
hw->irq = irq;
|
hw->irq = irq;
|
||||||
hw->ack_intr = ack_intr;
|
hw->ack_intr = ack_intr;
|
||||||
/*
|
|
||||||
* hw->iops = iops;
|
|
||||||
*/
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@@ -194,17 +194,6 @@ struct ide_drive_s;
|
|||||||
int ide_register_hw(hw_regs_t *, void (*)(struct ide_drive_s *),
|
int ide_register_hw(hw_regs_t *, void (*)(struct ide_drive_s *),
|
||||||
struct hwif_s **);
|
struct hwif_s **);
|
||||||
|
|
||||||
void ide_setup_ports( hw_regs_t *hw,
|
|
||||||
unsigned long base,
|
|
||||||
int *offsets,
|
|
||||||
unsigned long ctrl,
|
|
||||||
unsigned long intr,
|
|
||||||
ide_ack_intr_t *ack_intr,
|
|
||||||
#if 0
|
|
||||||
ide_io_ops_t *iops,
|
|
||||||
#endif
|
|
||||||
int irq);
|
|
||||||
|
|
||||||
static inline void ide_std_init_ports(hw_regs_t *hw,
|
static inline void ide_std_init_ports(hw_regs_t *hw,
|
||||||
unsigned long io_addr,
|
unsigned long io_addr,
|
||||||
unsigned long ctl_addr)
|
unsigned long ctl_addr)
|
||||||
|
Reference in New Issue
Block a user