e1000: Enable custom configuration bits for 82571/2 controllers
Enable custom configuration bits for 82571/2 controllers. The bits are required for correct functionality of these controllers. Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com> Signed-off-by: Ganesh Venkatesan <ganesh.venkatesan@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
committed by
Jeff Garzik
parent
24025e4ecf
commit
2ae76d98fb
@@ -1151,6 +1151,7 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter,
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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memset(txdr->buffer_info, 0, size);
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memset(txdr->buffer_info, 0, size);
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memset(&txdr->previous_buffer_info, 0, sizeof(struct e1000_buffer));
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/* round up to nearest 4K */
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/* round up to nearest 4K */
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@@ -1199,6 +1200,7 @@ setup_tx_desc_die:
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txdr->next_to_use = 0;
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txdr->next_to_use = 0;
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txdr->next_to_clean = 0;
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txdr->next_to_clean = 0;
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spin_lock_init(&txdr->tx_lock);
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return 0;
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return 0;
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}
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}
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@@ -1312,6 +1314,19 @@ e1000_configure_tx(struct e1000_adapter *adapter)
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E1000_WRITE_REG(hw, TCTL, tctl);
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E1000_WRITE_REG(hw, TCTL, tctl);
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if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
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tarc = E1000_READ_REG(hw, TARC0);
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tarc |= ((1 << 25) | (1 << 21));
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E1000_WRITE_REG(hw, TARC0, tarc);
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tarc = E1000_READ_REG(hw, TARC1);
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tarc |= (1 << 25);
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if (tctl & E1000_TCTL_MULR)
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tarc &= ~(1 << 28);
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else
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tarc |= (1 << 28);
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E1000_WRITE_REG(hw, TARC1, tarc);
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}
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e1000_config_collision_dist(hw);
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e1000_config_collision_dist(hw);
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/* Setup Transmit Descriptor Settings for eop descriptor */
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/* Setup Transmit Descriptor Settings for eop descriptor */
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@@ -1601,6 +1616,14 @@ e1000_configure_rx(struct e1000_adapter *adapter)
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1000000000 / (adapter->itr * 256));
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1000000000 / (adapter->itr * 256));
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}
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}
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if (hw->mac_type >= e1000_82571) {
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/* Reset delay timers after every interrupt */
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ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
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ctrl_ext |= E1000_CTRL_EXT_CANC;
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E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
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E1000_WRITE_FLUSH(hw);
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}
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/* Setup the HW Rx Head and Tail Descriptor Pointers and
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/* Setup the HW Rx Head and Tail Descriptor Pointers and
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* the Base and Length of the Rx Descriptor Ring */
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* the Base and Length of the Rx Descriptor Ring */
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switch (adapter->num_queues) {
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switch (adapter->num_queues) {
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