IB/ipath: Fix some white space and code style issues

This patch makes some white space changes and minor non-functional
changes to more closely match the code in OFED-1.3.

Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Ralph Campbell 2008-04-16 21:09:29 -07:00 committed by Roland Dreier
parent afd9970f95
commit 2ba3f56eb4
6 changed files with 38 additions and 35 deletions

View File

@ -627,7 +627,8 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
goto bail;
bail_irqsetup:
if (pdev->irq) free_irq(pdev->irq, dd);
if (pdev->irq)
free_irq(pdev->irq, dd);
bail_iounmap:
iounmap((volatile void __iomem *) dd->ipath_kregbase);
@ -1704,7 +1705,10 @@ int ipath_create_rcvhdrq(struct ipath_devdata *dd,
void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
{
ipath_dbg("Cancelling all in-progress send buffers\n");
dd->ipath_lastcancel = jiffies+HZ/2; /* skip armlaunch errs a bit */
/* skip armlaunch errs for a while */
dd->ipath_lastcancel = jiffies + HZ / 2;
/*
* the abort bit is auto-clearing. We read scratch to be sure
* that cancels and the abort have taken effect in the chip.
@ -2070,9 +2074,8 @@ void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
dd->ipath_led_override_timer.data = (unsigned long) dd;
dd->ipath_led_override_timer.expires = jiffies + 1;
add_timer(&dd->ipath_led_override_timer);
} else {
} else
atomic_dec(&dd->ipath_led_override_timer_active);
}
}
/**
@ -2220,12 +2223,12 @@ void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
"ipath_port0_skbinfo @ %p\n", pd->port_port,
skbinfo);
for (e = 0; e < dd->ipath_rcvegrcnt; e++)
if (skbinfo[e].skb) {
pci_unmap_single(dd->pcidev, skbinfo[e].phys,
dd->ipath_ibmaxlen,
PCI_DMA_FROMDEVICE);
dev_kfree_skb(skbinfo[e].skb);
}
if (skbinfo[e].skb) {
pci_unmap_single(dd->pcidev, skbinfo[e].phys,
dd->ipath_ibmaxlen,
PCI_DMA_FROMDEVICE);
dev_kfree_skb(skbinfo[e].skb);
}
vfree(skbinfo);
}
kfree(pd->port_tid_pg_list);
@ -2468,10 +2471,10 @@ void ipath_hol_event(unsigned long opaque)
int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
{
u64 val;
if ( new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK ) {
if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
return -1;
}
if ( dd->ipath_rx_pol_inv != new_pol_inv ) {
if (dd->ipath_rx_pol_inv != new_pol_inv) {
dd->ipath_rx_pol_inv = new_pol_inv;
val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<

View File

@ -645,7 +645,6 @@ static int init_housekeeping(struct ipath_devdata *dd,
return ret;
}
/**
* ipath_init_chip - do the actual initialization sequence on the chip
* @dd: the infinipath device
@ -754,7 +753,7 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
dd->ipath_f_early_init(dd);
/*
* cancel any possible active sends from early driver load.
* Cancel any possible active sends from early driver load.
* Follows early_init because some chips have to initialize
* PIO buffers in early_init to avoid false parity errors.
*/
@ -884,7 +883,7 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
&dd->pcidev->dev, pd->port_rcvhdrq_size,
&dd->ipath_dummy_hdrq_phys,
gfp_flags);
if (!dd->ipath_dummy_hdrq ) {
if (!dd->ipath_dummy_hdrq) {
dev_info(&dd->pcidev->dev,
"Couldn't allocate 0x%lx bytes for dummy hdrq\n",
pd->port_rcvhdrq_size);
@ -899,7 +898,7 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
*/
ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
if(!dd->ipath_stats_timer_active) {
if (!dd->ipath_stats_timer_active) {
/*
* first init, or after an admin disable/enable
* set up stats retrieval timer, even if we had errors

View File

@ -590,18 +590,19 @@ static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
* ones on this particular interrupt, which also isn't great
*/
dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
dd->ipath_errormask &= ~dd->ipath_maskederrs;
ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
dd->ipath_errormask);
dd->ipath_errormask);
s_iserr = ipath_decode_err(msg, sizeof msg,
dd->ipath_maskederrs);
dd->ipath_maskederrs);
if (dd->ipath_maskederrs &
~(INFINIPATH_E_RRCVEGRFULL |
INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
~(INFINIPATH_E_RRCVEGRFULL |
INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
ipath_dev_err(dd, "Temporarily disabling "
"error(s) %llx reporting; too frequent (%s)\n",
(unsigned long long)dd->ipath_maskederrs,
(unsigned long long) dd->ipath_maskederrs,
msg);
else {
/*
@ -786,7 +787,6 @@ static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
return chkerrpkts;
}
/*
* try to cleanup as much as possible for anything that might have gone
* wrong while in freeze mode, such as pio buffers being written by user
@ -974,6 +974,7 @@ static void handle_urcv(struct ipath_devdata *dd, u32 istat)
dd->ipath_i_rcvurg_mask);
for (i = 1; i < dd->ipath_cfgports; i++) {
struct ipath_portdata *pd = dd->ipath_pd[i];
if (portr & (1 << i) && pd && pd->port_cnt) {
if (test_and_clear_bit(IPATH_PORT_WAITING_RCV,
&pd->port_flag)) {
@ -1095,8 +1096,7 @@ irqreturn_t ipath_intr(int irq, void *data)
gpiostatus = ipath_read_kreg32(
dd, dd->ipath_kregs->kr_gpio_status);
/* First the error-counter case.
*/
/* First the error-counter case. */
if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
(dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
/* want to clear the bits we see asserted. */

View File

@ -811,7 +811,7 @@ void ipath_hol_event(unsigned long);
*/
/* chip can report link latency (IB 1.2) */
#define IPATH_HAS_LINK_LATENCY 0x1
/* The chip is up and initted */
/* The chip is up and initted */
#define IPATH_INITTED 0x2
/* set if any user code has set kr_rcvhdrsize */
#define IPATH_RCVHDRSZ_SET 0x4
@ -1147,7 +1147,7 @@ extern struct mutex ipath_mutex;
# define __IPATH_DBG_WHICH(which,fmt,...) \
do { \
if(unlikely(ipath_debug&(which))) \
if (unlikely(ipath_debug & (which))) \
printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
__func__,##__VA_ARGS__); \
} while(0)

View File

@ -186,8 +186,8 @@
#define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3
#define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
#define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
#define INFINIPATH_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
#define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
#define INFINIPATH_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
#define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
#define INFINIPATH_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
#define INFINIPATH_IBCC_LINKCMD_SHIFT 18
#define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL

View File

@ -293,8 +293,8 @@ void ipath_get_faststats(unsigned long opaque)
iserr = ipath_decode_err(ebuf, sizeof ebuf,
dd->ipath_maskederrs);
if (dd->ipath_maskederrs &
~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
INFINIPATH_E_PKTERRS ))
~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
INFINIPATH_E_PKTERRS))
ipath_dev_err(dd, "Re-enabling masked errors "
"(%s)\n", ebuf);
else {
@ -306,17 +306,18 @@ void ipath_get_faststats(unsigned long opaque)
* level.
*/
if (iserr)
ipath_dbg("Re-enabling queue full errors (%s)\n",
ebuf);
ipath_dbg(
"Re-enabling queue full errors (%s)\n",
ebuf);
else
ipath_cdbg(ERRPKT, "Re-enabling packet"
" problem interrupt (%s)\n", ebuf);
" problem interrupt (%s)\n", ebuf);
}
/* re-enable masked errors */
dd->ipath_errormask |= dd->ipath_maskederrs;
ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
dd->ipath_errormask);
dd->ipath_errormask);
dd->ipath_maskederrs = 0;
}