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[ARM] 4503/1: nommu: Add noMMU support for ARMv7

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This patch adds the necessary ifdef's to the proc-v7.S code and
defines the v7wbi_tlb_fns macro in pgtable-nommu.h

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas
2007-07-20 11:43:02 +01:00
committed by Russell King
parent 7092fc38ee
commit 2eb8c82bc4
3 changed files with 16 additions and 12 deletions
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2
arch/arm/mm/Kconfig
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@@ -377,7 +377,7 @@ config CPU_V7
select CPU_CACHE_V7 select CPU_CACHE_V7
select CPU_CACHE_VIPT select CPU_CACHE_VIPT
select CPU_CP15_MMU select CPU_CP15_MMU
select CPU_HAS_ASID select CPU_HAS_ASID if MMU
select CPU_COPY_V6 if MMU select CPU_COPY_V6 if MMU
select CPU_TLB_V7 if MMU select CPU_TLB_V7 if MMU

23
arch/arm/mm/proc-v7.S
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@@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area)
* - we are not using split page tables * - we are not using split page tables
*/ */
ENTRY(cpu_v7_switch_mm) ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
mov r2, #0 mov r2, #0
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
@@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm)
isb isb
mcr p15, 0, r1, c13, c0, 1 @ set context ID mcr p15, 0, r1, c13, c0, 1 @ set context ID
isb isb
#endif
mov pc, lr mov pc, lr
/* /*
@@ -109,6 +111,7 @@ ENTRY(cpu_v7_switch_mm)
* 1111 0 1 1 r/w r/w * 1111 0 1 1 r/w r/w
*/ */
ENTRY(cpu_v7_set_pte_ext) ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version str r1, [r0], #-2048 @ linux version
bic r3, r1, #0x000003f0 bic r3, r1, #0x000003f0
@@ -136,6 +139,7 @@ ENTRY(cpu_v7_set_pte_ext)
str r3, [r0] str r3, [r0]
mcr p15, 0, r0, c7, c10, 1 @ flush_pte mcr p15, 0, r0, c7, c10, 1 @ flush_pte
#endif
mov pc, lr mov pc, lr
cpu_v7_name: cpu_v7_name:
@@ -169,6 +173,7 @@ __v7_setup:
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
#endif #endif
dsb dsb
#ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
mcr p15, 0, r10, c2, c0, 2 @ TTB control register mcr p15, 0, r10, c2, c0, 2 @ TTB control register
orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
@@ -176,11 +181,12 @@ __v7_setup:
mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
mov r10, #0x1f @ domains 0, 1 = manager mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register mcr p15, 0, r10, c3, c0, 0 @ load domain access register
#endif
adr r5, v7_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
ldr r10, cr1_clear @ get mask for bits to clear bic r0, r0, r5 @ clear bits them
bic r0, r0, r10 @ clear bits them orr r0, r0, r6 @ set them
ldr r10, cr1_set @ get mask for bits to set
orr r0, r0, r10 @ set them
mov pc, lr @ return to head.S:__ret mov pc, lr @ return to head.S:__ret
/* /*
@@ -189,12 +195,9 @@ __v7_setup:
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 0 110 0011 1.00 .111 1101 < we want * 0 110 0011 1.00 .111 1101 < we want
*/ */
.type cr1_clear, #object .type v7_crval, #object
.type cr1_set, #object v7_crval:
cr1_clear: crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
.word 0x0120c302
cr1_set:
.word 0x00c0387d
__v7_setup_stack: __v7_setup_stack:
.space 4 * 11 @ 11 registers .space 4 * 11 @ 11 registers

1
include/asm-arm/pgtable-nommu.h
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@@ -103,6 +103,7 @@ extern int is_in_rom(unsigned long);
#define v4wb_tlb_fns (0) #define v4wb_tlb_fns (0)
#define v4wbi_tlb_fns (0) #define v4wbi_tlb_fns (0)
#define v6wbi_tlb_fns (0) #define v6wbi_tlb_fns (0)
#define v7wbi_tlb_fns (0)
#define v3_user_fns (0) #define v3_user_fns (0)
#define v4_user_fns (0) #define v4_user_fns (0)