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[PATCH] ppc32: add 440GX erratum 440_43 workaround

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This patch adds workaround for PPC 440GX erratum 440_43. According to
this erratum spurious MachineChecks (caused by L1 cache parity) can
happen during DataTLB miss processing. We disable L1 cache parity
checking for 440GX rev.C and rev.F

Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Eugene Surovegin
2006-04-25 01:22:44 -07:00
committed by Paul Mackerras
parent 1269277a5e
commit 30aacebed0
4 changed files with 18 additions and 2 deletions
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13
arch/ppc/syslib/ibm440gx_common.c
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@@ -2,7 +2,7 @@
* PPC440GX system library
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
* Copyright (c) 2003 - 2006 Zultys Technologies
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -282,3 +282,14 @@ int ibm440gx_show_cpuinfo(struct seq_file *m){
return 0;
}
void __init ibm440gx_platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6,
unsigned long r7)
{
/* Erratum 440_43 workaround, disable L1 cache parity checking */
if (!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") ||
!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. F"))
mtspr(SPRN_CCR1, mfspr(SPRN_CCR1) | CCR1_DPC);
ibm44x_platform_init(r3, r4, r5, r6, r7);
}