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MIPS: Fix core number detection for MT cores

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In cores which implement the MT ASE, the CPUNum in the EBase register is
a concatenation of the core number & the VPE ID within that core. In
order to retrieve the correct core number CPUNum must be shifted
appropriately to remove the VPE ID bits.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
2014-03-27 10:57:30 +00:00
committed by Ralf Baechle
parent 968a0734db
commit 30ee615bb8
1 changed files with 5 additions and 1 deletions
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6
arch/mips/kernel/cpu-probe.c
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@@ -23,6 +23,7 @@
#include <asm/cpu-type.h> #include <asm/cpu-type.h>
#include <asm/fpu.h> #include <asm/fpu.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/msa.h> #include <asm/msa.h>
#include <asm/watch.h> #include <asm/watch.h>
#include <asm/elf.h> #include <asm/elf.h>
@@ -421,8 +422,11 @@ static void decode_configs(struct cpuinfo_mips *c)
mips_probe_watch_registers(c); mips_probe_watch_registers(c);
#ifndef CONFIG_MIPS_CPS #ifndef CONFIG_MIPS_CPS
if (cpu_has_mips_r2) if (cpu_has_mips_r2) {
c->core = read_c0_ebase() & 0x3ff; c->core = read_c0_ebase() & 0x3ff;
if (cpu_has_mipsmt)
c->core >>= fls(core_nvpes()) - 1;
}
#endif #endif
} }