iwlwifi: TX setup fix confusion between TX queue and TX DMA channel
This patch configures correctly TX DMA channel. It is not the same as TX queue. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Acked-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
committed by
John W. Linville
parent
25e35a56d5
commit
31a73fe4f3
@@ -692,9 +692,9 @@ static const u16 default_queue_to_tx_fifo[] = {
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static int iwl4965_alive_notify(struct iwl_priv *priv)
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static int iwl4965_alive_notify(struct iwl_priv *priv)
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{
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{
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u32 a;
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u32 a;
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int i = 0;
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unsigned long flags;
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unsigned long flags;
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int ret;
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int ret;
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int i, chan;
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spin_lock_irqsave(&priv->lock, flags);
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spin_lock_irqsave(&priv->lock, flags);
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@@ -718,6 +718,12 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
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iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
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priv->scd_bc_tbls.dma >> 10);
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priv->scd_bc_tbls.dma >> 10);
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/* Enable DMA channel */
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for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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/* Disable chain mode for all queues */
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/* Disable chain mode for all queues */
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iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
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iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
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@@ -748,7 +754,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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(1 << priv->hw_params.max_txq_num) - 1);
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(1 << priv->hw_params.max_txq_num) - 1);
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/* Activate all Tx DMA/FIFO channels */
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
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iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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@@ -700,9 +700,9 @@ static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
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static int iwl5000_alive_notify(struct iwl_priv *priv)
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static int iwl5000_alive_notify(struct iwl_priv *priv)
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{
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{
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u32 a;
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u32 a;
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int i = 0;
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unsigned long flags;
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unsigned long flags;
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int ret;
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int ret;
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int i, chan;
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spin_lock_irqsave(&priv->lock, flags);
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spin_lock_irqsave(&priv->lock, flags);
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@@ -725,6 +725,13 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
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iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
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iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
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priv->scd_bc_tbls.dma >> 10);
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priv->scd_bc_tbls.dma >> 10);
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/* Enable DMA channel */
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for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
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iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
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IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
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IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
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iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
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iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
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@@ -449,11 +449,6 @@ static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
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iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
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iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
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txq->q.dma_addr >> 8);
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txq->q.dma_addr >> 8);
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/* Enable DMA channel, using same id as for TFD queue */
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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iwl_release_nic_access(priv);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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