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Blackfin arch: introduce an IM_MEM macro to kgdb

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create an IN_MEM() macro to simplify comparing an address in an on-chip
region of memory and make things readable

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger
2008-11-18 17:48:22 +08:00
committed by Bryan Wu
parent 89c6c139a5
commit 31fba6e752
1 changed files with 35 additions and 70 deletions
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105
arch/blackfin/kernel/kgdb.c
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@@ -34,6 +34,15 @@ int gdb_bfin_vector = -1;
#error change the definition of slavecpulocks #error change the definition of slavecpulocks
#endif #endif
#define IN_MEM(addr, size, l1_addr, l1_size) \
({ \
unsigned long __addr = (unsigned long)(addr); \
(__addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
})
#define ASYNC_BANK_SIZE \
(ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{ {
gdb_regs[BFIN_R0] = regs->r0; gdb_regs[BFIN_R0] = regs->r0;
@@ -462,55 +471,32 @@ static int validate_memory_access_address(unsigned long addr, int size)
return 0; return 0;
if (addr >= SYSMMR_BASE) if (addr >= SYSMMR_BASE)
return 0; return 0;
if (addr >= ASYNC_BANK0_BASE if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
&& addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
return 0; return 0;
if (cpu == 0) { if (cpu == 0) {
if (addr >= L1_SCRATCH_START if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
&& (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
return 0; return 0;
#if L1_CODE_LENGTH != 0 if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH))
if (addr >= L1_CODE_START
&& (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
return 0; return 0;
#endif if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
#if L1_DATA_A_LENGTH != 0
if (addr >= L1_DATA_A_START
&& (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
return 0; return 0;
#endif if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
#if L1_DATA_B_LENGTH != 0
if (addr >= L1_DATA_B_START
&& (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
return 0; return 0;
#endif
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
} else if (cpu == 1) { } else if (cpu == 1) {
if (addr >= COREB_L1_SCRATCH_START if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
&& (addr + size <= COREB_L1_SCRATCH_START
+ L1_SCRATCH_LENGTH))
return 0; return 0;
# if L1_CODE_LENGTH != 0 if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
if (addr >= COREB_L1_CODE_START
&& (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
return 0; return 0;
# endif if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
# if L1_DATA_A_LENGTH != 0
if (addr >= COREB_L1_DATA_A_START
&& (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
return 0; return 0;
# endif if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
# if L1_DATA_B_LENGTH != 0
if (addr >= COREB_L1_DATA_B_START
&& (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
return 0; return 0;
# endif
#endif #endif
} }
#if L2_LENGTH != 0 #if L2_LENGTH
if (addr >= L2_START if (IN_MEM(addr, size, L2_START, L2_LENGTH))
&& addr + size <= L2_START + L2_LENGTH)
return 0; return 0;
#endif #endif
@@ -566,12 +552,9 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
default: default:
err = EFAULT; err = EFAULT;
} }
} else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
(unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
|| (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
(unsigned int)(mem + count) <=
COREB_L1_CODE_START + L1_CODE_LENGTH)
#endif #endif
) { ) {
/* access L1 instruction SRAM*/ /* access L1 instruction SRAM*/
@@ -642,12 +625,9 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
default: default:
return EFAULT; return EFAULT;
} }
} else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
(unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
|| (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
(unsigned int)(mem + count) <=
COREB_L1_CODE_START + L1_CODE_LENGTH)
#endif #endif
) { ) {
/* access L1 instruction SRAM */ /* access L1 instruction SRAM */
@@ -707,12 +687,9 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
default: default:
return EFAULT; return EFAULT;
} }
} else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
(unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
|| (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
(unsigned int)(mem + count) <=
COREB_L1_CODE_START + L1_CODE_LENGTH)
#endif #endif
) { ) {
/* access L1 instruction SRAM */ /* access L1 instruction SRAM */
@@ -729,22 +706,16 @@ int kgdb_validate_break_address(unsigned long addr)
if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end) if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
return 0; return 0;
if (addr >= ASYNC_BANK0_BASE if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
&& addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
return 0; return 0;
#if L1_CODE_LENGTH != 0 if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
if (cpu == 0 && addr >= L1_CODE_START
&& addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
return 0; return 0;
# ifdef CONFIG_SMP #ifdef CONFIG_SMP
else if (cpu == 1 && addr >= COREB_L1_CODE_START else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
&& addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
return 0; return 0;
# endif
#endif #endif
#if L2_LENGTH != 0 #if L2_LENGTH
if (addr >= L2_START if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
&& addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
return 0; return 0;
#endif #endif
@@ -756,13 +727,9 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
int err; int err;
int cpu = raw_smp_processor_id(); int cpu = raw_smp_processor_id();
if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
&& (unsigned int)(addr + BREAK_INSTR_SIZE)
<= L1_CODE_START + L1_CODE_LENGTH)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
|| (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
&& (unsigned int)(addr + BREAK_INSTR_SIZE)
<= COREB_L1_CODE_START + L1_CODE_LENGTH)
#endif #endif
) { ) {
/* access L1 instruction SRAM */ /* access L1 instruction SRAM */
@@ -788,9 +755,7 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
{ {
if ((unsigned int)addr >= L1_CODE_START && if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) {
(unsigned int)(addr + BREAK_INSTR_SIZE) <=
L1_CODE_START + L1_CODE_LENGTH) {
/* access L1 instruction SRAM */ /* access L1 instruction SRAM */
if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
return -EFAULT; return -EFAULT;