m32r: Rearrange platform-dependent codes
Rearrange platform-dependent codes from arch/m32r/kernel/*.c
to arch/m32r/platforms/{platform}/.
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
This commit is contained in:
Hirokazu Takata
9
arch/m32r/platforms/Makefile
Normal file
9
arch/m32r/platforms/Makefile
Normal file
@@ -0,0 +1,9 @@
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# arch/m32r/platforms/Makefile
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obj-$(CONFIG_PLAT_M32104UT) += m32104ut/
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obj-$(CONFIG_PLAT_M32700UT) += m32700ut/
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obj-$(CONFIG_PLAT_MAPPI) += mappi/
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obj-$(CONFIG_PLAT_MAPPI2) += mappi2/
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obj-$(CONFIG_PLAT_MAPPI3) += mappi3/
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obj-$(CONFIG_PLAT_OAKS32R) += oaks32r/
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obj-$(CONFIG_PLAT_OPSPUT) += opsput/
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obj-$(CONFIG_PLAT_USRV) += usrv/
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1
arch/m32r/platforms/m32104ut/Makefile
Normal file
1
arch/m32r/platforms/m32104ut/Makefile
Normal file
@@ -0,0 +1 @@
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obj-y := setup.o io.o
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297
arch/m32r/platforms/m32104ut/io.c
Normal file
297
arch/m32r/platforms/m32104ut/io.c
Normal file
@@ -0,0 +1,297 @@
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/*
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* linux/arch/m32r/platforms/m32104ut/io.c
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*
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* Typical I/O routines for M32104UT board.
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*
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* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Mamoru Sakugawa,
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* Naoto Sugai, Hayato Fujiwara
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*/
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#include <asm/m32r.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/byteorder.h>
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#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
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#include <linux/types.h>
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#define M32R_PCC_IOMAP_SIZE 0x1000
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#define M32R_PCC_IOSTART0 0x1000
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#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
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extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
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extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
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extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
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extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
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#define PORT2ADDR(port) _port2addr(port)
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | NONCACHE_OFFSET);
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}
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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static inline void *__port2addr_ata(unsigned long port)
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{
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static int dummy_reg;
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switch (port) {
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case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
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case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
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case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
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case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
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case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
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case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
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case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
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case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
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case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
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default: return (void *)&dummy_reg;
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}
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}
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#endif
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/*
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* M32104T-LAN is located in the extended bus space
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* from 0x01000000 to 0x01ffffff on physical address.
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* The base address of LAN controller(LAN91C111) is 0x300.
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*/
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#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
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#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
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static inline void *_port2addr_ne(unsigned long port)
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{
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return (void *)(port + NONCACHE_OFFSET + 0x01000000);
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}
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static inline void delay(void)
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{
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__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
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}
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/*
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* NIC I/O function
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*/
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#define PORT2ADDR_NE(port) _port2addr_ne(port)
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static inline unsigned char _ne_inb(void *portp)
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{
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return *(volatile unsigned char *)portp;
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}
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static inline unsigned short _ne_inw(void *portp)
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{
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return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
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}
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static inline void _ne_insb(void *portp, void *addr, unsigned long count)
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{
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unsigned char *buf = (unsigned char *)addr;
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while (count--)
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*buf++ = _ne_inb(portp);
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}
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static inline void _ne_outb(unsigned char b, void *portp)
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{
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*(volatile unsigned char *)portp = b;
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}
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static inline void _ne_outw(unsigned short w, void *portp)
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{
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*(volatile unsigned short *)portp = cpu_to_le16(w);
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}
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unsigned char _inb(unsigned long port)
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{
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if (port >= LAN_IOSTART && port < LAN_IOEND)
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return _ne_inb(PORT2ADDR_NE(port));
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return *(volatile unsigned char *)PORT2ADDR(port);
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}
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unsigned short _inw(unsigned long port)
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{
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if (port >= LAN_IOSTART && port < LAN_IOEND)
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return _ne_inw(PORT2ADDR_NE(port));
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return *(volatile unsigned short *)PORT2ADDR(port);
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}
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unsigned long _inl(unsigned long port)
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{
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return *(volatile unsigned long *)PORT2ADDR(port);
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}
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unsigned char _inb_p(unsigned long port)
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{
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unsigned char v = _inb(port);
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delay();
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return (v);
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}
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unsigned short _inw_p(unsigned long port)
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{
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unsigned short v = _inw(port);
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delay();
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return (v);
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}
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unsigned long _inl_p(unsigned long port)
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{
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unsigned long v = _inl(port);
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delay();
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return (v);
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}
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void _outb(unsigned char b, unsigned long port)
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{
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if (port >= LAN_IOSTART && port < LAN_IOEND)
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_ne_outb(b, PORT2ADDR_NE(port));
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else
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*(volatile unsigned char *)PORT2ADDR(port) = b;
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}
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void _outw(unsigned short w, unsigned long port)
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{
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if (port >= LAN_IOSTART && port < LAN_IOEND)
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_ne_outw(w, PORT2ADDR_NE(port));
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else
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*(volatile unsigned short *)PORT2ADDR(port) = w;
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}
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void _outl(unsigned long l, unsigned long port)
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{
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*(volatile unsigned long *)PORT2ADDR(port) = l;
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}
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void _outb_p(unsigned char b, unsigned long port)
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{
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_outb(b, port);
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delay();
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}
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void _outw_p(unsigned short w, unsigned long port)
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{
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_outw(w, port);
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delay();
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}
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void _outl_p(unsigned long l, unsigned long port)
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{
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_outl(l, port);
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delay();
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}
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void _insb(unsigned int port, void *addr, unsigned long count)
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{
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if (port >= LAN_IOSTART && port < LAN_IOEND)
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_ne_insb(PORT2ADDR_NE(port), addr, count);
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else {
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unsigned char *buf = addr;
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unsigned char *portp = PORT2ADDR(port);
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while (count--)
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*buf++ = *(volatile unsigned char *)portp;
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}
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}
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void _insw(unsigned int port, void *addr, unsigned long count)
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{
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unsigned short *buf = addr;
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unsigned short *portp;
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if (port >= LAN_IOSTART && port < LAN_IOEND) {
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/*
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* This portion is only used by smc91111.c to read data
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* from the DATA_REG. Do not swap the data.
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*/
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portp = PORT2ADDR_NE(port);
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while (count--)
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*buf++ = *(volatile unsigned short *)portp;
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#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
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} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
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pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
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count, 1);
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#endif
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
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portp = __port2addr_ata(port);
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while (count--)
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*buf++ = *(volatile unsigned short *)portp;
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#endif
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} else {
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portp = PORT2ADDR(port);
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while (count--)
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*buf++ = *(volatile unsigned short *)portp;
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}
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}
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void _insl(unsigned int port, void *addr, unsigned long count)
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{
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unsigned long *buf = addr;
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unsigned long *portp;
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portp = PORT2ADDR(port);
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while (count--)
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*buf++ = *(volatile unsigned long *)portp;
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}
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void _outsb(unsigned int port, const void *addr, unsigned long count)
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{
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const unsigned char *buf = addr;
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unsigned char *portp;
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if (port >= LAN_IOSTART && port < LAN_IOEND) {
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portp = PORT2ADDR_NE(port);
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while (count--)
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_ne_outb(*buf++, portp);
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} else {
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portp = PORT2ADDR(port);
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while (count--)
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*(volatile unsigned char *)portp = *buf++;
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}
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}
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void _outsw(unsigned int port, const void *addr, unsigned long count)
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{
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const unsigned short *buf = addr;
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unsigned short *portp;
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if (port >= LAN_IOSTART && port < LAN_IOEND) {
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/*
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* This portion is only used by smc91111.c to write data
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* into the DATA_REG. Do not swap the data.
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*/
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portp = PORT2ADDR_NE(port);
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while (count--)
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*(volatile unsigned short *)portp = *buf++;
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
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portp = __port2addr_ata(port);
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while (count--)
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*(volatile unsigned short *)portp = *buf++;
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#endif
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#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
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} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
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pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
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count, 1);
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#endif
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} else {
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portp = PORT2ADDR(port);
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while (count--)
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*(volatile unsigned short *)portp = *buf++;
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}
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}
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void _outsl(unsigned int port, const void *addr, unsigned long count)
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{
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const unsigned long *buf = addr;
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unsigned char *portp;
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portp = PORT2ADDR(port);
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while (count--)
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*(volatile unsigned long *)portp = *buf++;
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}
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155
arch/m32r/platforms/m32104ut/setup.c
Normal file
155
arch/m32r/platforms/m32104ut/setup.c
Normal file
@@ -0,0 +1,155 @@
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/*
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* linux/arch/m32r/platforms/m32104ut/setup.c
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*
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* Setup routines for M32104UT Board
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*
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* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Mamoru Sakugawa,
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* Naoto Sugai, Hayato Fujiwara
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
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icu_data_t icu_data[NR_IRQS];
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static void disable_m32104ut_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
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outl(data, port);
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}
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static void enable_m32104ut_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
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outl(data, port);
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}
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static void mask_and_ack_m32104ut(unsigned int irq)
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{
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disable_m32104ut_irq(irq);
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}
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static void end_m32104ut_irq(unsigned int irq)
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{
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enable_m32104ut_irq(irq);
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}
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static unsigned int startup_m32104ut_irq(unsigned int irq)
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{
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enable_m32104ut_irq(irq);
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return (0);
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}
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static void shutdown_m32104ut_irq(unsigned int irq)
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{
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unsigned long port;
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port = irq2port(irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct hw_interrupt_type m32104ut_irq_type =
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{
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.typename = "M32104UT-IRQ",
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.startup = startup_m32104ut_irq,
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.shutdown = shutdown_m32104ut_irq,
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.enable = enable_m32104ut_irq,
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.disable = disable_m32104ut_irq,
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.ack = mask_and_ack_m32104ut,
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.end = end_m32104ut_irq
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};
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void __init init_IRQ(void)
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{
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static int once = 0;
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if (once)
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return;
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else
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once++;
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#if defined(CONFIG_SMC91X)
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/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
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irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_INT0].action = 0;
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irq_desc[M32R_IRQ_INT0].depth = 1;
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icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
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disable_m32104ut_irq(M32R_IRQ_INT0);
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#endif /* CONFIG_SMC91X */
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|
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/* MFT2 : system timer */
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irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_MFT2].action = 0;
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irq_desc[M32R_IRQ_MFT2].depth = 1;
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_m32104ut_irq(M32R_IRQ_MFT2);
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|
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#ifdef CONFIG_SERIAL_M32R_SIO
|
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/* SIO0_R : uart receive data */
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irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
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irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type;
|
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irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
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irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
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icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
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disable_m32104ut_irq(M32R_IRQ_SIO0_R);
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/* SIO0_S : uart send data */
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irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
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irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
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icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
|
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disable_m32104ut_irq(M32R_IRQ_SIO0_S);
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||||
#endif /* CONFIG_SERIAL_M32R_SIO */
|
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}
|
||||
|
||||
#if defined(CONFIG_SMC91X)
|
||||
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||||
#define LAN_IOSTART 0x300
|
||||
#define LAN_IOEND 0x320
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (LAN_IOSTART),
|
||||
.end = (LAN_IOEND),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = M32R_IRQ_INT0,
|
||||
.end = M32R_IRQ_INT0,
|
||||
.flags = IORESOURCE_IRQ,
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||||
}
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
platform_device_register(&smc91x_device);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
1
arch/m32r/platforms/m32700ut/Makefile
Normal file
1
arch/m32r/platforms/m32700ut/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
395
arch/m32r/platforms/m32700ut/io.c
Normal file
395
arch/m32r/platforms/m32700ut/io.c
Normal file
@@ -0,0 +1,395 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/m32700ut/io.c
|
||||
*
|
||||
* Typical I/O routines for M32700UT board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Takeo Takahashi
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file "COPYING" in the main directory of this
|
||||
* archive for more details.
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
#include <linux/types.h>
|
||||
|
||||
#define M32R_PCC_IOMAP_SIZE 0x1000
|
||||
|
||||
#define M32R_PCC_IOSTART0 0x1000
|
||||
#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
|
||||
|
||||
extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
#define PORT2ADDR_USB(port) _port2addr_usb(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
return (void *)(port | NONCACHE_OFFSET);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
static inline void *__port2addr_ata(unsigned long port)
|
||||
{
|
||||
static int dummy_reg;
|
||||
|
||||
switch (port) {
|
||||
case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
|
||||
case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
|
||||
case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
|
||||
case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
|
||||
case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
|
||||
case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
|
||||
case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
|
||||
case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
|
||||
case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
|
||||
default: return (void *)&dummy_reg;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* M32700UT-LAN is located in the extended bus space
|
||||
* from 0x10000000 to 0x13ffffff on physical address.
|
||||
* The base address of LAN controller(LAN91C111) is 0x300.
|
||||
*/
|
||||
#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
|
||||
#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)(port + 0x10000000);
|
||||
}
|
||||
static inline void *_port2addr_usb(unsigned long port)
|
||||
{
|
||||
return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
|
||||
}
|
||||
|
||||
static inline void _ne_insb(void *portp, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned char *buf = (unsigned char *)addr;
|
||||
|
||||
while (count--)
|
||||
*buf++ = _ne_inb(portp);
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned char *)portp = b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = cpu_to_le16(w);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned char *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned char b;
|
||||
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
#endif
|
||||
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned short *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
else if(port >= 0x340 && port < 0x3a0)
|
||||
return *(volatile unsigned short *)PORT2ADDR_USB(port);
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned short w;
|
||||
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned long l;
|
||||
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned char *)__port2addr_ata(port) = b;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned short *)__port2addr_ata(port) = w;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
if(port >= 0x340 && port < 0x3a0)
|
||||
*(volatile unsigned short *)PORT2ADDR_USB(port) = w;
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
}
|
||||
#endif
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
/*
|
||||
* This portion is only used by smc91111.c to read data
|
||||
* from the DATA_REG. Do not swap the data.
|
||||
*/
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
/*
|
||||
* This portion is only used by smc91111.c to write data
|
||||
* into the DATA_REG. Do not swap the data.
|
||||
*/
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
518
arch/m32r/platforms/m32700ut/setup.c
Normal file
518
arch/m32r/platforms/m32700ut/setup.c
Normal file
@@ -0,0 +1,518 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/m32700ut/setup.c
|
||||
*
|
||||
* Setup routines for Renesas M32700UT Board
|
||||
*
|
||||
* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Takeo Takahashi
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file "COPYING" in the main directory of this
|
||||
* archive for more details.
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/*
|
||||
* M32700 Interrupt Control Unit (Level 1)
|
||||
*/
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
|
||||
|
||||
static void disable_m32700ut_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_m32700ut_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_m32700ut(unsigned int irq)
|
||||
{
|
||||
disable_m32700ut_irq(irq);
|
||||
}
|
||||
|
||||
static void end_m32700ut_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_m32700ut_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_m32700ut_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type m32700ut_irq_type =
|
||||
{
|
||||
.typename = "M32700UT-IRQ",
|
||||
.startup = startup_m32700ut_irq,
|
||||
.shutdown = shutdown_m32700ut_irq,
|
||||
.enable = enable_m32700ut_irq,
|
||||
.disable = disable_m32700ut_irq,
|
||||
.ack = mask_and_ack_m32700ut,
|
||||
.end = end_m32700ut_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on M32700UT (Level 2)
|
||||
*/
|
||||
#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
|
||||
#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
typedef struct {
|
||||
unsigned short icucr; /* ICU Control Register */
|
||||
} pld_icu_data_t;
|
||||
|
||||
static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
|
||||
|
||||
static void disable_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
// disable_m32700ut_irq(M32R_IRQ_INT1);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
// enable_m32700ut_irq(M32R_IRQ_INT1);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_m32700ut_pld(unsigned int irq)
|
||||
{
|
||||
disable_m32700ut_pld_irq(irq);
|
||||
// mask_and_ack_m32700ut(M32R_IRQ_INT1);
|
||||
}
|
||||
|
||||
static void end_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_pld_irq(irq);
|
||||
end_m32700ut_irq(M32R_IRQ_INT1);
|
||||
}
|
||||
|
||||
static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_pld_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
// shutdown_m32700ut_irq(M32R_IRQ_INT1);
|
||||
port = pldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type m32700ut_pld_irq_type =
|
||||
{
|
||||
.typename = "M32700UT-PLD-IRQ",
|
||||
.startup = startup_m32700ut_pld_irq,
|
||||
.shutdown = shutdown_m32700ut_pld_irq,
|
||||
.enable = enable_m32700ut_pld_irq,
|
||||
.disable = disable_m32700ut_pld_irq,
|
||||
.ack = mask_and_ack_m32700ut_pld,
|
||||
.end = end_m32700ut_pld_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
|
||||
*/
|
||||
#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
|
||||
#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
|
||||
|
||||
static void disable_m32700ut_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_m32700ut_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
|
||||
{
|
||||
disable_m32700ut_lanpld_irq(irq);
|
||||
}
|
||||
|
||||
static void end_m32700ut_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_lanpld_irq(irq);
|
||||
end_m32700ut_irq(M32R_IRQ_INT0);
|
||||
}
|
||||
|
||||
static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_lanpld_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type m32700ut_lanpld_irq_type =
|
||||
{
|
||||
.typename = "M32700UT-PLD-LAN-IRQ",
|
||||
.startup = startup_m32700ut_lanpld_irq,
|
||||
.shutdown = shutdown_m32700ut_lanpld_irq,
|
||||
.enable = enable_m32700ut_lanpld_irq,
|
||||
.disable = disable_m32700ut_lanpld_irq,
|
||||
.ack = mask_and_ack_m32700ut_lanpld,
|
||||
.end = end_m32700ut_lanpld_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
|
||||
*/
|
||||
#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
|
||||
#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
|
||||
|
||||
static void disable_m32700ut_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_m32700ut_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
|
||||
{
|
||||
disable_m32700ut_lcdpld_irq(irq);
|
||||
}
|
||||
|
||||
static void end_m32700ut_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_lcdpld_irq(irq);
|
||||
end_m32700ut_irq(M32R_IRQ_INT2);
|
||||
}
|
||||
|
||||
static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_lcdpld_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
|
||||
{
|
||||
.typename = "M32700UT-PLD-LCD-IRQ",
|
||||
.startup = startup_m32700ut_lcdpld_irq,
|
||||
.shutdown = shutdown_m32700ut_lcdpld_irq,
|
||||
.enable = enable_m32700ut_lcdpld_irq,
|
||||
.disable = disable_m32700ut_lcdpld_irq,
|
||||
.ack = mask_and_ack_m32700ut_lcdpld,
|
||||
.end = end_m32700ut_lcdpld_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
|
||||
irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
|
||||
irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
|
||||
irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
|
||||
irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
|
||||
lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
|
||||
disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = 0;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_m32700ut_irq(M32R_IRQ_MFT2);
|
||||
|
||||
/* SIO0 : receive */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_m32700ut_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0 : send */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_m32700ut_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1 : receive */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_m32700ut_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1 : send */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_m32700ut_irq(M32R_IRQ_SIO1_S);
|
||||
|
||||
/* DMA1 : */
|
||||
irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_DMA1].action = 0;
|
||||
irq_desc[M32R_IRQ_DMA1].depth = 1;
|
||||
icu_data[M32R_IRQ_DMA1].icucr = 0;
|
||||
disable_m32700ut_irq(M32R_IRQ_DMA1);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_PLDSIO
|
||||
/* INT#1: SIO0 Receive on PLD */
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
|
||||
|
||||
/* INT#1: SIO0 Send on PLD */
|
||||
irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_SIO0_SND].action = 0;
|
||||
irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
|
||||
#endif /* CONFIG_SERIAL_M32R_PLDSIO */
|
||||
|
||||
/* INT#1: CFC IREQ on PLD */
|
||||
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CFIREQ].action = 0;
|
||||
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
|
||||
|
||||
/* INT#1: CFC Insert on PLD */
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
|
||||
|
||||
/* INT#1: CFC Eject on PLD */
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
|
||||
|
||||
/*
|
||||
* INT0# is used for LAN, DIO
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
enable_m32700ut_irq(M32R_IRQ_INT0);
|
||||
|
||||
/*
|
||||
* INT1# is used for UART, MMC, CF Controller in FPGA.
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
enable_m32700ut_irq(M32R_IRQ_INT1);
|
||||
|
||||
#if defined(CONFIG_USB)
|
||||
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
|
||||
|
||||
irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
|
||||
irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
|
||||
irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
|
||||
irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
|
||||
lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
|
||||
disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
|
||||
#endif
|
||||
/*
|
||||
* INT2# is used for BAT, USB, AUDIO
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
|
||||
enable_m32700ut_irq(M32R_IRQ_INT2);
|
||||
|
||||
#if defined(CONFIG_VIDEO_M32R_AR)
|
||||
/*
|
||||
* INT3# is used for AR
|
||||
*/
|
||||
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
|
||||
irq_desc[M32R_IRQ_INT3].action = 0;
|
||||
irq_desc[M32R_IRQ_INT3].depth = 1;
|
||||
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_m32700ut_irq(M32R_IRQ_INT3);
|
||||
#endif /* CONFIG_VIDEO_M32R_AR */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SMC91X)
|
||||
|
||||
#define LAN_IOSTART 0x300
|
||||
#define LAN_IOEND 0x320
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (LAN_IOSTART),
|
||||
.end = (LAN_IOEND),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = M32700UT_LAN_IRQ_LAN,
|
||||
.end = M32700UT_LAN_IRQ_LAN,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
|
||||
#include <video/s1d13xxxfb.h>
|
||||
#include <asm/s1d13806.h>
|
||||
|
||||
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
|
||||
.initregs = s1d13xxxfb_initregs,
|
||||
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
|
||||
.platform_init_video = NULL,
|
||||
#ifdef CONFIG_PM
|
||||
.platform_suspend_video = NULL,
|
||||
.platform_resume_video = NULL,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s1d13xxxfb_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x10600000UL,
|
||||
.end = 0x1073FFFFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x10400000UL,
|
||||
.end = 0x104001FFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device s1d13xxxfb_device = {
|
||||
.name = S1D_DEVICENAME,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &s1d13xxxfb_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
|
||||
.resource = s1d13xxxfb_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
platform_device_register(&smc91x_device);
|
||||
#endif
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
platform_device_register(&s1d13xxxfb_device);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
1
arch/m32r/platforms/mappi/Makefile
Normal file
1
arch/m32r/platforms/mappi/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
325
arch/m32r/platforms/mappi/io.c
Normal file
325
arch/m32r/platforms/mappi/io.c
Normal file
@@ -0,0 +1,325 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/mappi/io.c
|
||||
*
|
||||
* Typical I/O routines for Mappi board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
#include <linux/types.h>
|
||||
|
||||
#define M32R_PCC_IOMAP_SIZE 0x1000
|
||||
|
||||
#define M32R_PCC_IOSTART0 0x1000
|
||||
#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
|
||||
#define M32R_PCC_IOSTART1 0x2000
|
||||
#define M32R_PCC_IOEND1 (M32R_PCC_IOSTART1 + M32R_PCC_IOMAP_SIZE - 1)
|
||||
|
||||
extern void pcc_ioread(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite(int, unsigned long, void *, size_t, size_t, int);
|
||||
#endif /* CONFIG_PCMCIA && CONFIG_M32R_PCC */
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
return (void *)(port | NONCACHE_OFFSET);
|
||||
}
|
||||
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)((port<<1) + NONCACHE_OFFSET + 0x0C000000);
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return (unsigned char) *(volatile unsigned short *)portp;
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
unsigned short tmp;
|
||||
|
||||
tmp = *(volatile unsigned short *)portp;
|
||||
return le16_to_cpu(tmp);
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = (unsigned short)b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = cpu_to_le16(w);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned char b;
|
||||
pcc_ioread(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
unsigned char b;
|
||||
pcc_ioread(1, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
#endif
|
||||
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned short w;
|
||||
pcc_ioread(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
unsigned short w;
|
||||
pcc_ioread(1, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned long l;
|
||||
pcc_ioread(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
unsigned short l;
|
||||
pcc_ioread(1, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite(0, port, &b, sizeof(b), 1, 0);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_iowrite(1, port, &b, sizeof(b), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite(0, port, &w, sizeof(w), 1, 0);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_iowrite(1, port, &w, sizeof(w), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite(0, port, &l, sizeof(l), 1, 0);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_iowrite(1, port, &l, sizeof(l), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320){
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_ioread(1, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = _ne_inw(portp);
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread(0, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_ioread(1, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_iowrite(1, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outw(*buf++, portp);
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite(0, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
} else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
|
||||
pcc_iowrite(1, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
201
arch/m32r/platforms/mappi/setup.c
Normal file
201
arch/m32r/platforms/mappi/setup.c
Normal file
@@ -0,0 +1,201 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/mappi/setup.c
|
||||
*
|
||||
* Setup routines for Renesas MAPPI Board
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[NR_IRQS];
|
||||
|
||||
static void disable_mappi_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_mappi_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_mappi(unsigned int irq)
|
||||
{
|
||||
disable_mappi_irq(irq);
|
||||
}
|
||||
|
||||
static void end_mappi_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
|
||||
enable_mappi_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_mappi_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_mappi_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type mappi_irq_type =
|
||||
{
|
||||
.typename = "MAPPI-IRQ",
|
||||
.startup = startup_mappi_irq,
|
||||
.shutdown = shutdown_mappi_irq,
|
||||
.enable = enable_mappi_irq,
|
||||
.disable = disable_mappi_irq,
|
||||
.ack = mask_and_ack_mappi,
|
||||
.end = end_mappi_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
static int once = 0;
|
||||
|
||||
if (once)
|
||||
return;
|
||||
else
|
||||
once++;
|
||||
|
||||
#ifdef CONFIG_NE2000
|
||||
/* INT0 : LAN controller (RTL8019AS) */
|
||||
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_INT0].action = NULL;
|
||||
irq_desc[M32R_IRQ_INT0].depth = 1;
|
||||
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
disable_mappi_irq(M32R_IRQ_INT0);
|
||||
#endif /* CONFIG_M32R_NE2000 */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = NULL;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_mappi_irq(M32R_IRQ_MFT2);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_SIO
|
||||
/* SIO0_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = NULL;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = NULL;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = NULL;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = NULL;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO1_S);
|
||||
#endif /* CONFIG_SERIAL_M32R_SIO */
|
||||
|
||||
#if defined(CONFIG_M32R_PCC)
|
||||
/* INT1 : pccard0 interrupt */
|
||||
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_INT1].action = NULL;
|
||||
irq_desc[M32R_IRQ_INT1].depth = 1;
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
|
||||
disable_mappi_irq(M32R_IRQ_INT1);
|
||||
|
||||
/* INT2 : pccard1 interrupt */
|
||||
irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_INT2].action = NULL;
|
||||
irq_desc[M32R_IRQ_INT2].depth = 1;
|
||||
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
|
||||
disable_mappi_irq(M32R_IRQ_INT2);
|
||||
#endif /* CONFIG_M32RPCC */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
|
||||
#include <video/s1d13xxxfb.h>
|
||||
#include <asm/s1d13806.h>
|
||||
|
||||
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
|
||||
.initregs = s1d13xxxfb_initregs,
|
||||
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
|
||||
.platform_init_video = NULL,
|
||||
#ifdef CONFIG_PM
|
||||
.platform_suspend_video = NULL,
|
||||
.platform_resume_video = NULL,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s1d13xxxfb_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x10200000UL,
|
||||
.end = 0x1033FFFFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x10000000UL,
|
||||
.end = 0x100001FFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device s1d13xxxfb_device = {
|
||||
.name = S1D_DEVICENAME,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &s1d13xxxfb_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
|
||||
.resource = s1d13xxxfb_resources,
|
||||
};
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
platform_device_register(&s1d13xxxfb_device);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
#endif
|
||||
1
arch/m32r/platforms/mappi2/Makefile
Normal file
1
arch/m32r/platforms/mappi2/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
383
arch/m32r/platforms/mappi2/io.c
Normal file
383
arch/m32r/platforms/mappi2/io.c
Normal file
@@ -0,0 +1,383 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/mappi2/io.c
|
||||
*
|
||||
* Typical I/O routines for Mappi2 board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
#include <linux/types.h>
|
||||
|
||||
#define M32R_PCC_IOMAP_SIZE 0x1000
|
||||
|
||||
#define M32R_PCC_IOSTART0 0x1000
|
||||
#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
|
||||
|
||||
extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
#define PORT2ADDR_USB(port) _port2addr_usb(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
return (void *)(port | NONCACHE_OFFSET);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
static inline void *__port2addr_ata(unsigned long port)
|
||||
{
|
||||
static int dummy_reg;
|
||||
|
||||
switch (port) {
|
||||
case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
|
||||
case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
|
||||
case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
|
||||
case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
|
||||
case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
|
||||
case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
|
||||
case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
|
||||
case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
|
||||
case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
|
||||
default: return (void *)&dummy_reg;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
|
||||
#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
|
||||
#ifdef CONFIG_CHIP_OPSP
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)(port + 0x10000000);
|
||||
}
|
||||
#else
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)(port + 0x04000000);
|
||||
}
|
||||
#endif
|
||||
static inline void *_port2addr_usb(unsigned long port)
|
||||
{
|
||||
return (void *)(port + NONCACHE_OFFSET + 0x14000000);
|
||||
}
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return (unsigned char) *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
|
||||
}
|
||||
|
||||
static inline void _ne_insb(void *portp, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned char *buf = addr;
|
||||
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned char *)portp = (unsigned char)b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = cpu_to_le16(w);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned char *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned char b;
|
||||
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
#endif
|
||||
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned short *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
else if (port >= 0x340 && port < 0x3a0)
|
||||
return *(volatile unsigned short *)PORT2ADDR_USB(port);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned short w;
|
||||
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned long l;
|
||||
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned char *)__port2addr_ata(port) = b;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned short *)__port2addr_ata(port) = w;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
if (port >= 0x340 && port < 0x3a0)
|
||||
*(volatile unsigned short *)PORT2ADDR_USB(port) = w;
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
}
|
||||
#endif
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
201
arch/m32r/platforms/mappi2/setup.c
Normal file
201
arch/m32r/platforms/mappi2/setup.c
Normal file
@@ -0,0 +1,201 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/mappi2/setup.c
|
||||
*
|
||||
* Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[NR_IRQS];
|
||||
|
||||
static void disable_mappi2_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
if ((irq == 0) ||(irq >= NR_IRQS)) {
|
||||
printk("bad irq 0x%08x\n", irq);
|
||||
return;
|
||||
}
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_mappi2_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
if ((irq == 0) ||(irq >= NR_IRQS)) {
|
||||
printk("bad irq 0x%08x\n", irq);
|
||||
return;
|
||||
}
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_mappi2(unsigned int irq)
|
||||
{
|
||||
disable_mappi2_irq(irq);
|
||||
}
|
||||
|
||||
static void end_mappi2_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi2_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_mappi2_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi2_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_mappi2_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type mappi2_irq_type =
|
||||
{
|
||||
.typename = "MAPPI2-IRQ",
|
||||
.startup = startup_mappi2_irq,
|
||||
.shutdown = shutdown_mappi2_irq,
|
||||
.enable = enable_mappi2_irq,
|
||||
.disable = disable_mappi2_irq,
|
||||
.ack = mask_and_ack_mappi2,
|
||||
.end = end_mappi2_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
/* INT0 : LAN controller (SMC91111) */
|
||||
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_INT0].action = 0;
|
||||
irq_desc[M32R_IRQ_INT0].depth = 1;
|
||||
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_mappi2_irq(M32R_IRQ_INT0);
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = 0;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_mappi2_irq(M32R_IRQ_MFT2);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_SIO
|
||||
/* SIO0_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_mappi2_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_mappi2_irq(M32R_IRQ_SIO0_S);
|
||||
/* SIO1_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_mappi2_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_mappi2_irq(M32R_IRQ_SIO1_S);
|
||||
#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
|
||||
|
||||
#if defined(CONFIG_USB)
|
||||
/* INT1 : USB Host controller interrupt */
|
||||
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type;
|
||||
irq_desc[M32R_IRQ_INT1].action = 0;
|
||||
irq_desc[M32R_IRQ_INT1].depth = 1;
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
|
||||
disable_mappi2_irq(M32R_IRQ_INT1);
|
||||
#endif /* CONFIG_USB */
|
||||
|
||||
/* ICUCR40: CFC IREQ */
|
||||
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type;
|
||||
irq_desc[PLD_IRQ_CFIREQ].action = 0;
|
||||
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
|
||||
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
|
||||
disable_mappi2_irq(PLD_IRQ_CFIREQ);
|
||||
|
||||
#if defined(CONFIG_M32R_CFC)
|
||||
/* ICUCR41: CFC Insert */
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
|
||||
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
|
||||
disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
|
||||
|
||||
/* ICUCR42: CFC Eject */
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
|
||||
icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
|
||||
#endif /* CONFIG_MAPPI2_CFC */
|
||||
}
|
||||
|
||||
#define LAN_IOSTART 0x300
|
||||
#define LAN_IOEND 0x320
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (LAN_IOSTART),
|
||||
.end = (LAN_IOEND),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = M32R_IRQ_INT0,
|
||||
.end = M32R_IRQ_INT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
platform_device_register(&smc91x_device);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
1
arch/m32r/platforms/mappi3/Makefile
Normal file
1
arch/m32r/platforms/mappi3/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
405
arch/m32r/platforms/mappi3/io.c
Normal file
405
arch/m32r/platforms/mappi3/io.c
Normal file
@@ -0,0 +1,405 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/mappi3/io.c
|
||||
*
|
||||
* Typical I/O routines for Mappi3 board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
#include <linux/types.h>
|
||||
|
||||
#define M32R_PCC_IOMAP_SIZE 0x1000
|
||||
|
||||
#define M32R_PCC_IOSTART0 0x1000
|
||||
#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
|
||||
|
||||
extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
#define PORT2ADDR_USB(port) _port2addr_usb(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
return (void *)(port | NONCACHE_OFFSET);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IDE)
|
||||
static inline void *__port2addr_ata(unsigned long port)
|
||||
{
|
||||
static int dummy_reg;
|
||||
|
||||
switch (port) {
|
||||
/* IDE0 CF */
|
||||
case 0x1f0: return (void *)(0x14002000 | NONCACHE_OFFSET);
|
||||
case 0x1f1: return (void *)(0x14012800 | NONCACHE_OFFSET);
|
||||
case 0x1f2: return (void *)(0x14012002 | NONCACHE_OFFSET);
|
||||
case 0x1f3: return (void *)(0x14012802 | NONCACHE_OFFSET);
|
||||
case 0x1f4: return (void *)(0x14012004 | NONCACHE_OFFSET);
|
||||
case 0x1f5: return (void *)(0x14012804 | NONCACHE_OFFSET);
|
||||
case 0x1f6: return (void *)(0x14012006 | NONCACHE_OFFSET);
|
||||
case 0x1f7: return (void *)(0x14012806 | NONCACHE_OFFSET);
|
||||
case 0x3f6: return (void *)(0x1401200e | NONCACHE_OFFSET);
|
||||
/* IDE1 IDE */
|
||||
case 0x170: /* Data 16bit */
|
||||
return (void *)(0x14810000 | NONCACHE_OFFSET);
|
||||
case 0x171: /* Features / Error */
|
||||
return (void *)(0x14810002 | NONCACHE_OFFSET);
|
||||
case 0x172: /* Sector count */
|
||||
return (void *)(0x14810004 | NONCACHE_OFFSET);
|
||||
case 0x173: /* Sector number */
|
||||
return (void *)(0x14810006 | NONCACHE_OFFSET);
|
||||
case 0x174: /* Cylinder low */
|
||||
return (void *)(0x14810008 | NONCACHE_OFFSET);
|
||||
case 0x175: /* Cylinder high */
|
||||
return (void *)(0x1481000a | NONCACHE_OFFSET);
|
||||
case 0x176: /* Device head */
|
||||
return (void *)(0x1481000c | NONCACHE_OFFSET);
|
||||
case 0x177: /* Command */
|
||||
return (void *)(0x1481000e | NONCACHE_OFFSET);
|
||||
case 0x376: /* Device control / Alt status */
|
||||
return (void *)(0x1480800c | NONCACHE_OFFSET);
|
||||
|
||||
default: return (void *)&dummy_reg;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
|
||||
#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)(port + 0x10000000);
|
||||
}
|
||||
|
||||
static inline void *_port2addr_usb(unsigned long port)
|
||||
{
|
||||
return (void *)(port + NONCACHE_OFFSET + 0x12000000);
|
||||
}
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return (unsigned char) *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
|
||||
}
|
||||
|
||||
static inline void _ne_insb(void *portp, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned char *buf = addr;
|
||||
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned char *)portp = (unsigned char)b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = cpu_to_le16(w);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE)
|
||||
else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
return *(volatile unsigned char *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned char b;
|
||||
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE)
|
||||
else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
return *(volatile unsigned short *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
else if (port >= 0x340 && port < 0x3a0)
|
||||
return *(volatile unsigned short *)PORT2ADDR_USB(port);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned short w;
|
||||
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned long l;
|
||||
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE)
|
||||
if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
*(volatile unsigned char *)__port2addr_ata(port) = b;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE)
|
||||
if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
*(volatile unsigned short *)__port2addr_ata(port) = w;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
if (port >= 0x340 && port < 0x3a0)
|
||||
*(volatile unsigned short *)PORT2ADDR_USB(port) = w;
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
#if defined(CONFIG_IDE)
|
||||
else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
}
|
||||
#endif
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
#if defined(CONFIG_IDE)
|
||||
} else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
#if defined(CONFIG_IDE)
|
||||
} else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#if defined(CONFIG_IDE)
|
||||
} else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
|
||||
((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
251
arch/m32r/platforms/mappi3/setup.c
Normal file
251
arch/m32r/platforms/mappi3/setup.c
Normal file
@@ -0,0 +1,251 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/mappi3/setup.c
|
||||
*
|
||||
* Setup routines for Renesas MAPPI-III(M3A-2170) Board
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[NR_IRQS];
|
||||
|
||||
static void disable_mappi3_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
if ((irq == 0) ||(irq >= NR_IRQS)) {
|
||||
printk("bad irq 0x%08x\n", irq);
|
||||
return;
|
||||
}
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_mappi3_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
if ((irq == 0) ||(irq >= NR_IRQS)) {
|
||||
printk("bad irq 0x%08x\n", irq);
|
||||
return;
|
||||
}
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_mappi3(unsigned int irq)
|
||||
{
|
||||
disable_mappi3_irq(irq);
|
||||
}
|
||||
|
||||
static void end_mappi3_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi3_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_mappi3_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi3_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_mappi3_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type mappi3_irq_type =
|
||||
{
|
||||
.typename = "MAPPI3-IRQ",
|
||||
.startup = startup_mappi3_irq,
|
||||
.shutdown = shutdown_mappi3_irq,
|
||||
.enable = enable_mappi3_irq,
|
||||
.disable = disable_mappi3_irq,
|
||||
.ack = mask_and_ack_mappi3,
|
||||
.end = end_mappi3_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
/* INT0 : LAN controller (SMC91111) */
|
||||
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_INT0].action = 0;
|
||||
irq_desc[M32R_IRQ_INT0].depth = 1;
|
||||
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_mappi3_irq(M32R_IRQ_INT0);
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = 0;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_mappi3_irq(M32R_IRQ_MFT2);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_SIO
|
||||
/* SIO0_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_mappi3_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_mappi3_irq(M32R_IRQ_SIO0_S);
|
||||
/* SIO1_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_mappi3_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_mappi3_irq(M32R_IRQ_SIO1_S);
|
||||
#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
|
||||
|
||||
#if defined(CONFIG_USB)
|
||||
/* INT1 : USB Host controller interrupt */
|
||||
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
|
||||
irq_desc[M32R_IRQ_INT1].action = 0;
|
||||
irq_desc[M32R_IRQ_INT1].depth = 1;
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
|
||||
disable_mappi3_irq(M32R_IRQ_INT1);
|
||||
#endif /* CONFIG_USB */
|
||||
|
||||
/* CFC IREQ */
|
||||
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type;
|
||||
irq_desc[PLD_IRQ_CFIREQ].action = 0;
|
||||
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
|
||||
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
|
||||
disable_mappi3_irq(PLD_IRQ_CFIREQ);
|
||||
|
||||
#if defined(CONFIG_M32R_CFC)
|
||||
/* ICUCR41: CFC Insert & eject */
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
|
||||
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
|
||||
disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
|
||||
|
||||
#endif /* CONFIG_M32R_CFC */
|
||||
|
||||
/* IDE IREQ */
|
||||
irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type;
|
||||
irq_desc[PLD_IRQ_IDEIREQ].action = 0;
|
||||
irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
|
||||
icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_mappi3_irq(PLD_IRQ_IDEIREQ);
|
||||
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SMC91X)
|
||||
|
||||
#define LAN_IOSTART 0x300
|
||||
#define LAN_IOEND 0x320
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (LAN_IOSTART),
|
||||
.end = (LAN_IOEND),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = M32R_IRQ_INT0,
|
||||
.end = M32R_IRQ_INT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
|
||||
#include <video/s1d13xxxfb.h>
|
||||
#include <asm/s1d13806.h>
|
||||
|
||||
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
|
||||
.initregs = s1d13xxxfb_initregs,
|
||||
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
|
||||
.platform_init_video = NULL,
|
||||
#ifdef CONFIG_PM
|
||||
.platform_suspend_video = NULL,
|
||||
.platform_resume_video = NULL,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s1d13xxxfb_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x1d600000UL,
|
||||
.end = 0x1d73FFFFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x1d400000UL,
|
||||
.end = 0x1d4001FFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device s1d13xxxfb_device = {
|
||||
.name = S1D_DEVICENAME,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &s1d13xxxfb_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
|
||||
.resource = s1d13xxxfb_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
platform_device_register(&smc91x_device);
|
||||
#endif
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
platform_device_register(&s1d13xxxfb_device);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
1
arch/m32r/platforms/oaks32r/Makefile
Normal file
1
arch/m32r/platforms/oaks32r/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
228
arch/m32r/platforms/oaks32r/io.c
Normal file
228
arch/m32r/platforms/oaks32r/io.c
Normal file
@@ -0,0 +1,228 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/oaks32r/io.c
|
||||
*
|
||||
* Typical I/O routines for OAKS32R board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
return (void *)(port | NONCACHE_OFFSET);
|
||||
}
|
||||
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)((port<<1) + NONCACHE_OFFSET + 0x02000000);
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return *(volatile unsigned char *)(portp+1);
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
unsigned short tmp;
|
||||
|
||||
tmp = *(unsigned short *)(portp) & 0xff;
|
||||
tmp |= *(unsigned short *)(portp+2) << 8;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static inline void _ne_insb(void *portp, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned char *buf = addr;
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)(portp+1);
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned char *)(portp+1) = b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = (w >> 8);
|
||||
*(volatile unsigned short *)(portp+2) = (w & 0xff);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = _ne_inw(portp);
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outw(*buf++, portp);
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
135
arch/m32r/platforms/oaks32r/setup.c
Normal file
135
arch/m32r/platforms/oaks32r/setup.c
Normal file
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/oaks32r/setup.c
|
||||
*
|
||||
* Setup routines for OAKS32R Board
|
||||
*
|
||||
* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[NR_IRQS];
|
||||
|
||||
static void disable_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_mappi(unsigned int irq)
|
||||
{
|
||||
disable_oaks32r_irq(irq);
|
||||
}
|
||||
|
||||
static void end_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
enable_oaks32r_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
enable_oaks32r_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type oaks32r_irq_type =
|
||||
{
|
||||
.typename = "OAKS32R-IRQ",
|
||||
.startup = startup_oaks32r_irq,
|
||||
.shutdown = shutdown_oaks32r_irq,
|
||||
.enable = enable_oaks32r_irq,
|
||||
.disable = disable_oaks32r_irq,
|
||||
.ack = mask_and_ack_mappi,
|
||||
.end = end_oaks32r_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
static int once = 0;
|
||||
|
||||
if (once)
|
||||
return;
|
||||
else
|
||||
once++;
|
||||
|
||||
#ifdef CONFIG_NE2000
|
||||
/* INT3 : LAN controller (RTL8019AS) */
|
||||
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
|
||||
irq_desc[M32R_IRQ_INT3].action = 0;
|
||||
irq_desc[M32R_IRQ_INT3].depth = 1;
|
||||
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_oaks32r_irq(M32R_IRQ_INT3);
|
||||
#endif /* CONFIG_M32R_NE2000 */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = 0;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_oaks32r_irq(M32R_IRQ_MFT2);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_SIO
|
||||
/* SIO0_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO1_S);
|
||||
#endif /* CONFIG_SERIAL_M32R_SIO */
|
||||
}
|
||||
1
arch/m32r/platforms/opsput/Makefile
Normal file
1
arch/m32r/platforms/opsput/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
395
arch/m32r/platforms/opsput/io.c
Normal file
395
arch/m32r/platforms/opsput/io.c
Normal file
@@ -0,0 +1,395 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/opsput/io.c
|
||||
*
|
||||
* Typical I/O routines for OPSPUT board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Takeo Takahashi
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file "COPYING" in the main directory of this
|
||||
* archive for more details.
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
#include <linux/types.h>
|
||||
|
||||
#define M32R_PCC_IOMAP_SIZE 0x1000
|
||||
|
||||
#define M32R_PCC_IOSTART0 0x1000
|
||||
#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
|
||||
|
||||
extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
#define PORT2ADDR_USB(port) _port2addr_usb(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
return (void *)(port | NONCACHE_OFFSET);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
static inline void *__port2addr_ata(unsigned long port)
|
||||
{
|
||||
static int dummy_reg;
|
||||
|
||||
switch (port) {
|
||||
case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
|
||||
case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
|
||||
case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
|
||||
case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
|
||||
case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
|
||||
case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
|
||||
case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
|
||||
case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
|
||||
case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
|
||||
default: return (void *)&dummy_reg;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* OPSPUT-LAN is located in the extended bus space
|
||||
* from 0x10000000 to 0x13ffffff on physical address.
|
||||
* The base address of LAN controller(LAN91C111) is 0x300.
|
||||
*/
|
||||
#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
|
||||
#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
|
||||
static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)(port + 0x10000000);
|
||||
}
|
||||
static inline void *_port2addr_usb(unsigned long port)
|
||||
{
|
||||
return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
|
||||
}
|
||||
|
||||
static inline void _ne_insb(void *portp, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned char *buf = (unsigned char *)addr;
|
||||
|
||||
while (count--)
|
||||
*buf++ = _ne_inb(portp);
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned char *)portp = b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = cpu_to_le16(w);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned char *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned char b;
|
||||
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
#endif
|
||||
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned short *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
else if(port >= 0x340 && port < 0x3a0)
|
||||
return *(volatile unsigned short *)PORT2ADDR_USB(port);
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned short w;
|
||||
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned long l;
|
||||
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned char *)__port2addr_ata(port) = b;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned short *)__port2addr_ata(port) = w;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
if(port >= 0x340 && port < 0x3a0)
|
||||
*(volatile unsigned short *)PORT2ADDR_USB(port) = w;
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
}
|
||||
#endif
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
/*
|
||||
* This portion is only used by smc91111.c to read data
|
||||
* from the DATA_REG. Do not swap the data.
|
||||
*/
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
/*
|
||||
* This portion is only used by smc91111.c to write data
|
||||
* into the DATA_REG. Do not swap the data.
|
||||
*/
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
519
arch/m32r/platforms/opsput/setup.c
Normal file
519
arch/m32r/platforms/opsput/setup.c
Normal file
@@ -0,0 +1,519 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/opsput/setup.c
|
||||
*
|
||||
* Setup routines for Renesas OPSPUT Board
|
||||
*
|
||||
* Copyright (c) 2002-2005
|
||||
* Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file "COPYING" in the main directory of this
|
||||
* archive for more details.
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/*
|
||||
* OPSP Interrupt Control Unit (Level 1)
|
||||
*/
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
|
||||
|
||||
static void disable_opsput_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_opsput(unsigned int irq)
|
||||
{
|
||||
disable_opsput_irq(irq);
|
||||
}
|
||||
|
||||
static void end_opsput_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_opsput_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type opsput_irq_type =
|
||||
{
|
||||
.typename = "OPSPUT-IRQ",
|
||||
.startup = startup_opsput_irq,
|
||||
.shutdown = shutdown_opsput_irq,
|
||||
.enable = enable_opsput_irq,
|
||||
.disable = disable_opsput_irq,
|
||||
.ack = mask_and_ack_opsput,
|
||||
.end = end_opsput_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on OPSPUT (Level 2)
|
||||
*/
|
||||
#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
|
||||
#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
typedef struct {
|
||||
unsigned short icucr; /* ICU Control Register */
|
||||
} pld_icu_data_t;
|
||||
|
||||
static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
|
||||
|
||||
static void disable_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
// disable_opsput_irq(M32R_IRQ_INT1);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
// enable_opsput_irq(M32R_IRQ_INT1);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_opsput_pld(unsigned int irq)
|
||||
{
|
||||
disable_opsput_pld_irq(irq);
|
||||
// mask_and_ack_opsput(M32R_IRQ_INT1);
|
||||
}
|
||||
|
||||
static void end_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_pld_irq(irq);
|
||||
end_opsput_irq(M32R_IRQ_INT1);
|
||||
}
|
||||
|
||||
static unsigned int startup_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_pld_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
// shutdown_opsput_irq(M32R_IRQ_INT1);
|
||||
port = pldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type opsput_pld_irq_type =
|
||||
{
|
||||
.typename = "OPSPUT-PLD-IRQ",
|
||||
.startup = startup_opsput_pld_irq,
|
||||
.shutdown = shutdown_opsput_pld_irq,
|
||||
.enable = enable_opsput_pld_irq,
|
||||
.disable = disable_opsput_pld_irq,
|
||||
.ack = mask_and_ack_opsput_pld,
|
||||
.end = end_opsput_pld_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
|
||||
*/
|
||||
#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
|
||||
#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
|
||||
|
||||
static void disable_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_opsput_lanpld(unsigned int irq)
|
||||
{
|
||||
disable_opsput_lanpld_irq(irq);
|
||||
}
|
||||
|
||||
static void end_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_lanpld_irq(irq);
|
||||
end_opsput_irq(M32R_IRQ_INT0);
|
||||
}
|
||||
|
||||
static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_lanpld_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type opsput_lanpld_irq_type =
|
||||
{
|
||||
.typename = "OPSPUT-PLD-LAN-IRQ",
|
||||
.startup = startup_opsput_lanpld_irq,
|
||||
.shutdown = shutdown_opsput_lanpld_irq,
|
||||
.enable = enable_opsput_lanpld_irq,
|
||||
.disable = disable_opsput_lanpld_irq,
|
||||
.ack = mask_and_ack_opsput_lanpld,
|
||||
.end = end_opsput_lanpld_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
|
||||
*/
|
||||
#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
|
||||
#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
|
||||
|
||||
static void disable_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_opsput_lcdpld(unsigned int irq)
|
||||
{
|
||||
disable_opsput_lcdpld_irq(irq);
|
||||
}
|
||||
|
||||
static void end_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_lcdpld_irq(irq);
|
||||
end_opsput_irq(M32R_IRQ_INT2);
|
||||
}
|
||||
|
||||
static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
enable_opsput_lcdpld_irq(irq);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type opsput_lcdpld_irq_type =
|
||||
{
|
||||
"OPSPUT-PLD-LCD-IRQ",
|
||||
startup_opsput_lcdpld_irq,
|
||||
shutdown_opsput_lcdpld_irq,
|
||||
enable_opsput_lcdpld_irq,
|
||||
disable_opsput_lcdpld_irq,
|
||||
mask_and_ack_opsput_lcdpld,
|
||||
end_opsput_lcdpld_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
|
||||
irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
|
||||
irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type;
|
||||
irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
|
||||
irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
|
||||
lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
|
||||
disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = 0;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_opsput_irq(M32R_IRQ_MFT2);
|
||||
|
||||
/* SIO0 : receive */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0 : send */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1 : receive */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1 : send */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO1_S);
|
||||
|
||||
/* DMA1 : */
|
||||
irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_DMA1].action = 0;
|
||||
irq_desc[M32R_IRQ_DMA1].depth = 1;
|
||||
icu_data[M32R_IRQ_DMA1].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_DMA1);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_PLDSIO
|
||||
/* INT#1: SIO0 Receive on PLD */
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
|
||||
irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
|
||||
disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
|
||||
|
||||
/* INT#1: SIO0 Send on PLD */
|
||||
irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_SIO0_SND].action = 0;
|
||||
irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
|
||||
disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
|
||||
#endif /* CONFIG_SERIAL_M32R_PLDSIO */
|
||||
|
||||
/* INT#1: CFC IREQ on PLD */
|
||||
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CFIREQ].action = 0;
|
||||
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
|
||||
disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
|
||||
|
||||
/* INT#1: CFC Insert on PLD */
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
|
||||
disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
|
||||
|
||||
/* INT#1: CFC Eject on PLD */
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
|
||||
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
|
||||
disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
|
||||
|
||||
/*
|
||||
* INT0# is used for LAN, DIO
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
enable_opsput_irq(M32R_IRQ_INT0);
|
||||
|
||||
/*
|
||||
* INT1# is used for UART, MMC, CF Controller in FPGA.
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
enable_opsput_irq(M32R_IRQ_INT1);
|
||||
|
||||
#if defined(CONFIG_USB)
|
||||
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
|
||||
|
||||
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
|
||||
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type;
|
||||
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
|
||||
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
|
||||
lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
|
||||
disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
|
||||
#endif
|
||||
/*
|
||||
* INT2# is used for BAT, USB, AUDIO
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
|
||||
enable_opsput_irq(M32R_IRQ_INT2);
|
||||
|
||||
#if defined(CONFIG_VIDEO_M32R_AR)
|
||||
/*
|
||||
* INT3# is used for AR
|
||||
*/
|
||||
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type;
|
||||
irq_desc[M32R_IRQ_INT3].action = 0;
|
||||
irq_desc[M32R_IRQ_INT3].depth = 1;
|
||||
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_opsput_irq(M32R_IRQ_INT3);
|
||||
#endif /* CONFIG_VIDEO_M32R_AR */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SMC91X)
|
||||
|
||||
#define LAN_IOSTART 0x300
|
||||
#define LAN_IOEND 0x320
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (LAN_IOSTART),
|
||||
.end = (LAN_IOEND),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = OPSPUT_LAN_IRQ_LAN,
|
||||
.end = OPSPUT_LAN_IRQ_LAN,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
|
||||
#include <video/s1d13xxxfb.h>
|
||||
#include <asm/s1d13806.h>
|
||||
|
||||
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
|
||||
.initregs = s1d13xxxfb_initregs,
|
||||
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
|
||||
.platform_init_video = NULL,
|
||||
#ifdef CONFIG_PM
|
||||
.platform_suspend_video = NULL,
|
||||
.platform_resume_video = NULL,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s1d13xxxfb_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x10600000UL,
|
||||
.end = 0x1073FFFFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x10400000UL,
|
||||
.end = 0x104001FFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device s1d13xxxfb_device = {
|
||||
.name = S1D_DEVICENAME,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &s1d13xxxfb_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
|
||||
.resource = s1d13xxxfb_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
platform_device_register(&smc91x_device);
|
||||
#endif
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
platform_device_register(&s1d13xxxfb_device);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
1
arch/m32r/platforms/usrv/Makefile
Normal file
1
arch/m32r/platforms/usrv/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y := setup.o io.o
|
||||
225
arch/m32r/platforms/usrv/io.c
Normal file
225
arch/m32r/platforms/usrv/io.c
Normal file
@@ -0,0 +1,225 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/usrv/io.c
|
||||
*
|
||||
* Typical I/O routines for uServer board.
|
||||
*
|
||||
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Takeo Takahashi
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file "COPYING" in the main directory of this
|
||||
* archive for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "../../../../drivers/pcmcia/m32r_cfc.h"
|
||||
|
||||
extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
|
||||
extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
|
||||
#define CFC_IOSTART CFC_IOPORT_BASE
|
||||
#define CFC_IOEND (CFC_IOSTART + (M32R_PCC_MAPSIZE * M32R_MAX_PCC) - 1)
|
||||
|
||||
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
|
||||
#define UART0_REGSTART 0x04c20000
|
||||
#define UART1_REGSTART 0x04c20100
|
||||
#define UART_IOMAP_SIZE 8
|
||||
#define UART0_IOSTART 0x3f8
|
||||
#define UART0_IOEND (UART0_IOSTART + UART_IOMAP_SIZE - 1)
|
||||
#define UART1_IOSTART 0x2f8
|
||||
#define UART1_IOEND (UART1_IOSTART + UART_IOMAP_SIZE - 1)
|
||||
#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
|
||||
|
||||
#define PORT2ADDR(port) _port2addr(port)
|
||||
|
||||
static inline void *_port2addr(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
|
||||
if (port >= UART0_IOSTART && port <= UART0_IOEND)
|
||||
port = ((port - UART0_IOSTART) << 1) + UART0_REGSTART;
|
||||
else if (port >= UART1_IOSTART && port <= UART1_IOEND)
|
||||
port = ((port - UART1_IOSTART) << 1) + UART1_REGSTART;
|
||||
#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
|
||||
return (void *)(port | (NONCACHE_OFFSET));
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND) {
|
||||
unsigned char b;
|
||||
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND) {
|
||||
unsigned short w;
|
||||
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND) {
|
||||
unsigned long l;
|
||||
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
else
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
|
||||
else
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
|
||||
else
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_ioread_byte(0, port, addr, sizeof(unsigned char), count, 1);
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_ioread_word(0, port, addr, sizeof(unsigned short), count,
|
||||
1);
|
||||
else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void * addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= CFC_IOSTART && port <= CFC_IOEND)
|
||||
pcc_iowrite_word(0, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void * addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
248
arch/m32r/platforms/usrv/setup.c
Normal file
248
arch/m32r/platforms/usrv/setup.c
Normal file
@@ -0,0 +1,248 @@
|
||||
/*
|
||||
* linux/arch/m32r/platforms/usrv/setup.c
|
||||
*
|
||||
* Setup routines for MITSUBISHI uServer
|
||||
*
|
||||
* Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
|
||||
|
||||
static void disable_mappi_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_mappi_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_mappi(unsigned int irq)
|
||||
{
|
||||
disable_mappi_irq(irq);
|
||||
}
|
||||
|
||||
static void end_mappi_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_mappi_irq(unsigned int irq)
|
||||
{
|
||||
enable_mappi_irq(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void shutdown_mappi_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type mappi_irq_type =
|
||||
{
|
||||
.typename = "M32700-IRQ",
|
||||
.startup = startup_mappi_irq,
|
||||
.shutdown = shutdown_mappi_irq,
|
||||
.enable = enable_mappi_irq,
|
||||
.disable = disable_mappi_irq,
|
||||
.ack = mask_and_ack_mappi,
|
||||
.end = end_mappi_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on M32700UT (Level 2)
|
||||
*/
|
||||
#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
|
||||
#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
typedef struct {
|
||||
unsigned short icucr; /* ICU Control Register */
|
||||
} pld_icu_data_t;
|
||||
|
||||
static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
|
||||
|
||||
static void disable_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_and_ack_m32700ut_pld(unsigned int irq)
|
||||
{
|
||||
disable_m32700ut_pld_irq(irq);
|
||||
}
|
||||
|
||||
static void end_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_pld_irq(irq);
|
||||
end_mappi_irq(M32R_IRQ_INT1);
|
||||
}
|
||||
|
||||
static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
enable_m32700ut_pld_irq(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void shutdown_m32700ut_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
port = pldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type m32700ut_pld_irq_type =
|
||||
{
|
||||
.typename = "USRV-PLD-IRQ",
|
||||
.startup = startup_m32700ut_pld_irq,
|
||||
.shutdown = shutdown_m32700ut_pld_irq,
|
||||
.enable = enable_m32700ut_pld_irq,
|
||||
.disable = disable_m32700ut_pld_irq,
|
||||
.ack = mask_and_ack_m32700ut_pld,
|
||||
.end = end_m32700ut_pld_irq
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
static int once = 0;
|
||||
int i;
|
||||
|
||||
if (once)
|
||||
return;
|
||||
else
|
||||
once++;
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_MFT2].action = 0;
|
||||
irq_desc[M32R_IRQ_MFT2].depth = 1;
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_mappi_irq(M32R_IRQ_MFT2);
|
||||
|
||||
#if defined(CONFIG_SERIAL_M32R_SIO)
|
||||
/* SIO0_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO0_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1_R : uart receive data */
|
||||
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_R].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1_S : uart send data */
|
||||
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
|
||||
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
|
||||
irq_desc[M32R_IRQ_SIO1_S].action = 0;
|
||||
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_mappi_irq(M32R_IRQ_SIO1_S);
|
||||
#endif /* CONFIG_SERIAL_M32R_SIO */
|
||||
|
||||
/* INT#67-#71: CFC#0 IREQ on PLD */
|
||||
for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
|
||||
irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_CF0 + i].action = 0;
|
||||
irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
|
||||
= PLD_ICUCR_ISMOD01; /* 'L' level sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
|
||||
/* INT#76: 16552D#0 IREQ on PLD */
|
||||
irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_UART0].action = 0;
|
||||
irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
|
||||
= PLD_ICUCR_ISMOD03; /* 'H' level sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_UART0);
|
||||
|
||||
/* INT#77: 16552D#1 IREQ on PLD */
|
||||
irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_UART1].action = 0;
|
||||
irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
|
||||
= PLD_ICUCR_ISMOD03; /* 'H' level sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_UART1);
|
||||
#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
|
||||
|
||||
#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
|
||||
/* INT#80: AK4524 IREQ on PLD */
|
||||
irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
|
||||
irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type;
|
||||
irq_desc[PLD_IRQ_SNDINT].action = 0;
|
||||
irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
|
||||
= PLD_ICUCR_ISMOD01; /* 'L' level sense */
|
||||
disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
|
||||
#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
|
||||
|
||||
/*
|
||||
* INT1# is used for UART, MMC, CF Controller in FPGA.
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
|
||||
enable_mappi_irq(M32R_IRQ_INT1);
|
||||
}
|
||||
Reference in New Issue
Block a user