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tg3: Prevent send BD corruption

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On rare occasions, send BD corruptions can occur.  This patch
fixes the problem by increasing the L1 entry threshold to 4
milliseconds.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
2009-04-20 06:57:41 +00:00
committed by David S. Miller
parent df259d8cba
commit 33466d938f
2 changed files with 9 additions and 0 deletions
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7
drivers/net/tg3.c
View File

@@ -6717,6 +6717,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
tw32(TG3_CPMU_HST_ACC, val); tw32(TG3_CPMU_HST_ACC, val);
} }
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
PCIE_PWR_MGMT_L1_THRESH_4MS;
tw32(PCIE_PWR_MGMT_THRESH, val);
}
/* This works around an issue with Athlon chipsets on /* This works around an issue with Athlon chipsets on
* B3 tigon3 silicon. This bit has no effect on any * B3 tigon3 silicon. This bit has no effect on any
* other revision. But do not set this on PCI Express * other revision. But do not set this on PCI Express

2
drivers/net/tg3.h
View File

@@ -1697,6 +1697,8 @@
#define PCIE_PWR_MGMT_THRESH 0x00007d28 #define PCIE_PWR_MGMT_THRESH 0x00007d28
#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
/* OTP bit definitions */ /* OTP bit definitions */