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[POWERPC] Typo fixes interrrupt -> interrupt

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This fixes some interrrupt -> interrupt typos.

Signed-off-by: Gabriel Craciunescu <nix.or.die@googlemail.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Gabriel C
2007-08-01 19:41:09 +10:00
committed by Paul Mackerras
parent cc61f957f4
commit 33567a023e
4 changed files with 4 additions and 4 deletions
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2
arch/powerpc/platforms/embedded6xx/holly.c
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@@ -135,7 +135,7 @@ static void __init holly_setup_arch(void)
} }
/* /*
* Interrupt setup and service. Interrrupts on the holly come * Interrupt setup and service. Interrupts on the holly come
* from the four external INT pins, PCI interrupts are routed via * from the four external INT pins, PCI interrupts are routed via
* PCI interrupt control registers, it generates internal IRQ23 * PCI interrupt control registers, it generates internal IRQ23
* *

2
arch/powerpc/platforms/embedded6xx/linkstation.c
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@@ -99,7 +99,7 @@ static void __init linkstation_setup_arch(void)
} }
/* /*
* Interrupt setup and service. Interrrupts on the linkstation come * Interrupt setup and service. Interrupts on the linkstation come
* from the four PCI slots plus onboard 8241 devices: I2C, DUART. * from the four PCI slots plus onboard 8241 devices: I2C, DUART.
*/ */
static void __init linkstation_init_IRQ(void) static void __init linkstation_init_IRQ(void)

2
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
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@@ -91,7 +91,7 @@ static void __init mpc7448_hpc2_setup_arch(void)
} }
/* /*
* Interrupt setup and service. Interrrupts on the mpc7448_hpc2 come * Interrupt setup and service. Interrupts on the mpc7448_hpc2 come
* from the four external INT pins, PCI interrupts are routed via * from the four external INT pins, PCI interrupts are routed via
* PCI interrupt control registers, it generates internal IRQ23 * PCI interrupt control registers, it generates internal IRQ23
* *

2
arch/powerpc/platforms/iseries/it_lp_naca.h
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@@ -60,7 +60,7 @@ struct ItLpNaca {
u8 xRsvd2_0[128]; // Reserved x00-x7F u8 xRsvd2_0[128]; // Reserved x00-x7F
// CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators // CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators
// NB: Padding required to keep xInterrruptHdlr at x300 which is required // NB: Padding required to keep xInterruptHdlr at x300 which is required
// for v4r4 PLIC. // for v4r4 PLIC.
u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F
u8 xRsvd3_0[384]; // Reserved 180-2FF u8 xRsvd3_0[384]; // Reserved 180-2FF