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drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag

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Some asic revisions need to disable PG when UVD is active.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2013-07-03 15:14:25 -04:00
parent 62fa44bf7b
commit 338a95a955
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/radeon/sumo_dpm.c
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@@ -824,7 +824,9 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
if (pi->enable_gfx_power_gating) { if (pi->enable_gfx_power_gating) {
sumo_gfx_powergating_enable(rdev, true); if (!pi->disable_gfx_power_gating_in_uvd ||
!r600_is_uvd_state(new_rps->class, new_rps->class2))
sumo_gfx_powergating_enable(rdev, true);
} }
} }