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[MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board

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Signed-off-by: dmitry pervushin  <dpervushin@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
dmitry pervushin
2006-05-21 14:53:06 +04:00
committed by Ralf Baechle
parent 4a0312fca6
commit 355c471f2f
21 changed files with 3118 additions and 0 deletions
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1
arch/mips/pci/Makefile
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@ -18,6 +18,7 @@ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
#
# These are still pretty much in the old state, watch, go blind.

102
arch/mips/pci/fixup-emma2rh.c Normal file
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@ -0,0 +1,102 @@
/*
* arch/mips/pci/fixup-emma2rh.c
* This file defines the PCI configration.
*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/bootinfo.h>
#include <asm/debug.h>
#include <asm/emma2rh/emma2rh.h>
#define EMMA2RH_PCI_HOST_SLOT 0x09
#define EMMA2RH_USB_SLOT 0x03
#define PCI_DEVICE_ID_NEC_EMMA2RH 0x014b /* EMMA2RH PCI Host */
/*
* we fix up irqs based on the slot number.
* The first entry is at AD:11.
* Fortunately this works because, although we have two pci buses,
* they all have different slot numbers (except for rockhopper slot 20
* which is handled below).
*
*/
#define MAX_SLOT_NUM 10
static unsigned char irq_map[][5] __initdata = {
[3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
MARKEINS_PCI_IRQ_INTD, 0,},
[4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},
[5] = {0, 0, 0, 0, 0,},
[6] = {0, MARKEINS_PCI_IRQ_INTC, MARKEINS_PCI_IRQ_INTD,
MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,},
};
static void __devinit nec_usb_controller_fixup(struct pci_dev *dev)
{
if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT)
/* on board USB controller configuration */
pci_write_config_dword(dev, 0xe4, 1 << 5);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
nec_usb_controller_fixup);
/*
* Prevent the PCI layer from seeing the resources allocated to this device
* if it is the host bridge by marking it as such. These resources are of
* no consequence to the PCI layer (they are handled elsewhere).
*/
static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
{
int i;
if (PCI_SLOT(dev->devfn) == EMMA2RH_PCI_HOST_SLOT) {
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
emma2rh_pci_host_fixup);
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
return irq_map[slot][pin];
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}

186
arch/mips/pci/ops-emma2rh.c Normal file
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@ -0,0 +1,186 @@
/*
* arch/mips/pci/ops-emma2rh.c
* This file defines the PCI operation for EMMA2RH.
*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/pci/ops-vr41xx.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/debug.h>
#include <asm/emma2rh/emma2rh.h>
#define RTABORT (0x1<<9)
#define RMABORT (0x1<<10)
#define EMMA2RH_PCI_SLOT_NUM 9 /* 0000:09.0 is final PCI device */
/*
* access config space
*/
static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
{
/* check if the bus is top-level */
if (bus->parent != NULL) {
*bus_num = bus->number;
db_assert(bus_num != 0);
} else
*bus_num = 0;
if (*bus_num == 0) {
/* Type 0 */
if (PCI_SLOT(devfn) >= 10)
return PCIBIOS_DEVICE_NOT_FOUND;
} else {
/* Type 1 */
if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16))
return PCIBIOS_DEVICE_NOT_FOUND;
}
return 0;
}
static inline int set_pci_configuration_address(unsigned char bus_num,
unsigned int devfn, int where)
{
u32 config_win0;
emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT);
if (bus_num == 0)
/*
* Type 0 configuration
*/
config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9);
else
/*
* Type 1 configuration
*/
config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) |
(1 << 15) | (5 << 9);
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0);
return 0;
}
static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, uint32_t * val)
{
u32 bus_num;
u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
u32 backup_win0;
u32 data;
*val = 0xffffffffU;
if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
return PCIBIOS_DEVICE_NOT_FOUND;
backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
if (set_pci_configuration_address(bus_num, devfn, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
data =
*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
(where & 0xfffffffc));
switch (size) {
case 1:
*val = (data >> ((where & 3) << 3)) & 0xffU;
break;
case 2:
*val = (data >> ((where & 2) << 3)) & 0xffffU;
break;
case 4:
*val = data;
break;
default:
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
return PCIBIOS_FUNC_NOT_SUPPORTED;
}
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
u32 bus_num;
u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
u32 backup_win0;
u32 data;
int shift;
if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
return PCIBIOS_DEVICE_NOT_FOUND;
backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
if (set_pci_configuration_address(bus_num, devfn, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
/* read modify write */
data =
*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
(where & 0xfffffffc));
switch (size) {
case 1:
shift = (where & 3) << 3;
data &= ~(0xffU << shift);
data |= ((val & 0xffU) << shift);
break;
case 2:
shift = (where & 2) << 3;
data &= ~(0xffffU << shift);
data |= ((val & 0xffffU) << shift);
break;
case 4:
data = val;
break;
default:
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
return PCIBIOS_FUNC_NOT_SUPPORTED;
}
*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
(where & 0xfffffffc)) = data;
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops emma2rh_pci_ops = {
.read = pci_config_read,
.write = pci_config_write,
};

90
arch/mips/pci/pci-emma2rh.c Normal file
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@ -0,0 +1,90 @@
/*
* arch/mips/pci/pci-emma2rh.c
* This file defines the PCI configration.
*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/bootinfo.h>
#include <asm/debug.h>
#include <asm/emma2rh/emma2rh.h>
static struct resource pci_io_resource = {
.name = "pci IO space",
.start = EMMA2RH_PCI_IO_BASE,
.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO,
};
static struct resource pci_mem_resource = {
.name = "pci memory space",
.start = EMMA2RH_PCI_MEM_BASE,
.end = EMMA2RH_PCI_MEM_BASE + EMMA2RH_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
};
extern struct pci_ops emma2rh_pci_ops;
static struct pci_controller emma2rh_pci_controller = {
.pci_ops = &emma2rh_pci_ops,
.mem_resource = &pci_mem_resource,
.io_resource = &pci_io_resource,
.mem_offset = -0x04000000,
.io_offset = 0,
};
static void __init emma2rh_pci_init(void)
{
/* setup PCI interface */
emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f);
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18);
emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_COMMAND,
PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_CAP_LIST |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000);
emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000);
emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218);
emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600);
emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200);
emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200);
emma2rh_out32(EMMA2RH_PCI_TWIN_BADR, 0x00000000);
emma2rh_out32(EMMA2RH_PCI_TWIN0_DADR, 0x00000000);
emma2rh_out32(EMMA2RH_PCI_TWIN1_DADR, 0x00000000);
}
static int __init emma2rh_pci_setup(void)
{
emma2rh_pci_init();
register_pci_controller(&emma2rh_pci_controller);
return 0;
}
arch_initcall(emma2rh_pci_setup);